Page title matches

• semiconductor manufacturing process
  {{title|Semiconductor Manufacturing Process}} ...he series of steps used to create [[integrated circuits]]. The fabrication process comprises a series of [[chemical]]- and [[lithography]]-related steps where
  1 KB (173 words) - 10:26, 1 February 2019
• semiconductor fabrication process
  49 bytes (4 words) - 23:13, 31 January 2019

Page text matches

• WikiChip
  ...">'''WikiChip''' is the preeminent resource for computer architectures and semiconductor logic engineering, covering historical and contemporary electronic systems, <imagemap>Image:latest process.svg
  4 KB (394 words) - 12:00, 13 February 2020
• intel/mcs-4/4004
  |process=10 µm ...ww.intel.com/Assets/PDF/DataSheet/4004_datasheet.pdf 4004 Datasheet]</ref> process silicon-gate, capable of executing 92,000 instructions per second. The chip
  5 KB (748 words) - 21:37, 21 November 2021
• microprocessor
  [[File:IPO (input-process-output).svg|400px|right]] ...oarchitecture]] of the incorporated [[central processing unit|CPU]], the [[semiconductor]] technology involved, and the properties of the overall system. Some commo
  8 KB (1,149 words) - 00:41, 16 September 2019
• 10 µm lithography process
  ...e and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). |Process Name
  2 KB (177 words) - 23:04, 20 May 2018
• 6 µm lithography process
  ...y used by some semiconductor companies during the early to mid 1970s. This process was later superseded by [[5 µm]], [[3 µm]], and [[2 µm]] processes. |Process Name
  1 KB (119 words) - 23:04, 20 May 2018
• 3 µm lithography process
  ...thography process''' was the semiconductor process technology used by some semiconductor companies during the mid 1970s to the mid 1980s. | process 1 fab = [[Hitachi]]
  3 KB (314 words) - 23:04, 20 May 2018
• 2 µm lithography process
  ...some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by [[1.5 µm]], [[1.3 µm]], and [[1.2 µm]] processes. {{#invoke:process nodes
  8 KB (969 words) - 12:31, 22 February 2019
• 1.5 µm lithography process
  ...ngth of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by [[1.3 µm]], [[1.2 µm]], and [[1 µm]] processes. |Process Name
  3 KB (332 words) - 23:04, 20 May 2018
• 1 µm lithography process
  ...aphy process''' was the semiconductor process technology used by the major semiconductor companies between in the late 1980s. 1 µm was phased out in the early 1990 |Process Name
  1 KB (166 words) - 23:04, 20 May 2018
• 800 nm lithography process
  ...m process"''' refers to a process which has a gate length of 0.8 µm. This process was later replaced by [[650 nm]], [[600 nm]], and [[500 nm]] processes. |Process Name
  3 KB (272 words) - 23:04, 20 May 2018
• novix/nc4016
  |process=3 μm In 1988, the NC4016 design was licensed and improved by Harris Semiconductor which later rebranded the chip as the [[RTX2000]], a radiation hardened ver
  2 KB (257 words) - 16:31, 13 December 2017
• 8 µm lithography process
  ...ess at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes. The 8-micron process was used by Intel for many of their memory chips in the early 1970s such as
  5 KB (632 words) - 23:04, 20 May 2018
• fairchild/pps-25
  | developer = Fairchild Semiconductor | manufacturer = Fairchild Semiconductor
  2 KB (291 words) - 23:48, 10 July 2017
• fairchild/f9450
  The '''Fairchild F9450''' is a high-performance 16-bit [[bipolar process|bipolar]] [[microprocessor]] developed by [[Fairchild]] in 1985. The F9450, [[Category:Fairchild Semiconductor microprocessors]]
  2 KB (253 words) - 16:27, 20 December 2015
• mosfet
  {{title|MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor}}[[File:Electronic component mosfets.jpg|thumb|[[di ...ly the [[controlling gate|gate]] was made from metal, the name metal-oxide semiconductor (MOS) got stuck. Today, the gates are made of polycrystalline sillicon alth
  8 KB (1,362 words) - 23:38, 17 November 2015
• intel
  '''Intel Corporation''' is an American [[semiconductor]] company. While most notably known for their development of [[microprocess * {{\\|Process-Architecture-Optimization}} (PAO)
  9 KB (1,150 words) - 00:03, 2 October 2022
• national semiconductor/cops i
  | developer = National Semiconductor | manufacturer = National Semiconductor
  2 KB (274 words) - 18:29, 5 February 2016
• national semiconductor/cops ii
  | developer = National Semiconductor | manufacturer = National Semiconductor
  6 KB (685 words) - 22:49, 5 February 2016
• fairchild/9400
  | developer = Fairchild Semiconductor | manufacturer = Fairchild Semiconductor
  2 KB (223 words) - 23:04, 5 October 2017
• fairchild/4700
  | developer = Fairchild Semiconductor | manufacturer = Fairchild Semiconductor
  3 KB (283 words) - 17:18, 12 December 2016
• national semiconductor/maps
  | developer = National Semiconductor | manufacturer = National Semiconductor
  2 KB (276 words) - 18:29, 29 January 2016
• doping
  ...toms of impurities]] are intentionally introduced into an otherwise [[pure semiconductor]] in order to alter its optical and electronic properties.
  220 bytes (30 words) - 23:08, 5 August 2018
• rockwell international/pps-4
  | proc = <!-- process, e.g. "8 μm" --> [[National semiconductor]] later became a second source for the PPS-4.
  3 KB (359 words) - 17:26, 19 May 2016
• technology node
  ...nsistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor includ The driving force behind process node scaling is [[Moore's Law]]. To achieve density doubling, the [[contact
  8 KB (1,225 words) - 13:48, 14 December 2022
• 28 nm lithography process
  ...This technology superseded by commercial [[22 nm lithography process|22 nm process]]. | process 1 fab = [[TSMC]]
  6 KB (711 words) - 17:01, 26 March 2019
• 32 nm lithography process
  ...thography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. ...lled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patterning]].
  10 KB (1,090 words) - 19:14, 8 July 2021
• 14 nm lithography process
  ...4 nm node was introduced in 2014/2015 and has been replaced by the [[10 nm process]]. | process 1 fab = [[Intel]]
  17 KB (2,243 words) - 19:32, 25 May 2023
• 45 nm lithography process
  ...thography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010. ...time high-k + metal gate transistors was used in high-volume manufacturing process.
  5 KB (602 words) - 05:51, 20 July 2018
• 16 µm lithography process
  ...e and drain (Poly-SI channel implant). The typical [[wafer size]] for this process was 1.1-inch (28 mm). The standard transistor packages those years were the
  502 bytes (66 words) - 23:04, 20 May 2018
• 20 µm lithography process
  ...he source and drain (channel implant). The typical [[wafer]] size for this process was 0.875 inch (22 mm). The standard transistor packages those years were t
  902 bytes (119 words) - 23:04, 20 May 2018
• 50 µm lithography process
  ...y 50 µm between the source and drain. The typical [[wafer]] size for this process at companies such as [[Fairchild]] was 0.875 inch (22 mm). The standard tra
  524 bytes (70 words) - 23:04, 20 May 2018
• 22 nm lithography process
  ...process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015. ...te transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom
  7 KB (891 words) - 09:52, 25 November 2020
• 16 nm lithography process
  ...is technology is set to be replaced with [[10 nm lithography process|10 nm process]] in 2017. An enhanced version of TSMC's 16nm process was introduced in late 2016 called "12nm".
  4 KB (580 words) - 17:00, 26 March 2019
• 20 nm lithography process
  ...This technology superseded by commercial [[16 nm lithography process|16 nm process]]. | process 1 fab = [[TSMC]]
  4 KB (483 words) - 23:04, 20 May 2018
• 40 nm lithography process
  ...This technology superseded by commercial [[32 nm lithography process|32 nm process]] by 2010.
  2 KB (182 words) - 03:11, 17 August 2023
• 55 nm lithography process
  ...This technology superseded by commercial [[45 nm lithography process|45 nm process]].
  600 bytes (72 words) - 05:54, 20 July 2018
• 65 nm lithography process
  ...thography process|55 nm process]] (HN) / [[45 nm lithography process|45 nm process]] (FN) in 2007. |Process Name
  4 KB (407 words) - 05:55, 20 July 2018
• 130 nm lithography process
  ...rocess|110 nm process]] (HN) in 2003 and [[90 nm lithography process|90 nm process]] (FN) in 2004. |Process Name
  5 KB (500 words) - 16:02, 13 May 2020
• 90 nm lithography process
  ...thography process|80 nm process]] (HN) / [[65 nm lithography process|65 nm process]] (FN) in 2006. Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce [[strained silicon]] transi
  3 KB (354 words) - 03:09, 17 August 2023
• 180 nm lithography process
  ...cess|150 nm process]] (HN) in 2000 and [[130 nm lithography process|130 nm process]] (FN) in 2001. The 180 nm process was first to use Cu metalization as a replacement for Al for interconnects.
  4 KB (413 words) - 03:04, 17 August 2023
• 10 nm lithography process
  ...ode is currently being introduced and is set to get replaced by the [[7 nm process]] in 2018/2019. First introduced between 2017-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 3
  14 KB (1,903 words) - 06:52, 17 February 2023
• 7 nm lithography process
  ...[[integrated circuit]] fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timefram ...eature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production
  13 KB (1,941 words) - 02:40, 5 November 2022
• 5 nm lithography process
  ...process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin sometime around 2020. ...double patterning for the rest of the metal stack. Note that Intel [[7 nm process]] is comparable to the foundry 5-nanometer node.
  11 KB (1,662 words) - 02:58, 2 October 2022
• 250 nm lithography process
  ...ocess]] node. Commercial [[integrated circuit]] manufacturing using 250 nm process began in 1997 and was eventually replaced by [[180 nm]] by 1999. ...ed a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO₂]] dielectric and [
  6 KB (661 words) - 16:18, 21 August 2022
• 350 nm lithography process
  ...ocess]] node. Commercial [[integrated circuit]] manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by [[250 nm]] in 199 |Process Name
  5 KB (586 words) - 22:44, 4 April 2022
• 500 nm lithography process
  ...nm process]]. Commercial [[integrated circuit]] manufacturing using 500 nm process began in 1992. 500 nm and was phased out and later replaced by [[350 nm]] i |Process Name
  4 KB (438 words) - 06:15, 20 July 2018
• 600 nm lithography process
  ...ess used by some [[integrated circuit]] manufacturers in early 1990s. This process was later replaced by [[500 nm]] and [[350 nm]] processes. |Process Name
  1 KB (145 words) - 06:15, 20 July 2018
• 650 nm lithography process
  ...ess used by some [[integrated circuit]] manufacturers in early 1990s. This process was later replaced by [[500 nm]] and [[350 nm]] processes. |Process Name
  1 KB (131 words) - 06:15, 20 July 2018
• 1.2 µm lithography process
  ...aphy process''' was the semiconductor process technology used by the major semiconductor companies between in the late 1980s. 1 µm was phased out in the early 1990 |Process Name
  962 bytes (118 words) - 23:04, 20 May 2018
• 1.3 µm lithography process
  ...aphy process''' was the semiconductor process technology used by the major semiconductor companies between in the late 1980s. 1.3 µm was phased out from the late 1 |Process Name
  1 KB (138 words) - 12:57, 23 October 2022
• 110 nm lithography process
  ...process|130 nm]] and [[90 nm lithography process|90 nm]] processes. 110 nm process was used in the early 2000s. |Process Name
  1 KB (143 words) - 05:57, 20 July 2018
• 150 nm lithography process
  ...]] processes. Commercial [[integrated circuit]] manufacturing using 150 nm process began in early 2000s. This technology superseded by commercial [[130 nm]], ...or the production of 128 MiB, 256 MiB and [[Rambus]] [[DRAM]]s on a 150 nm process. Line 10 opened in the third quarter of [[2000]] producing 16,000 [[wafer s
  2 KB (238 words) - 02:56, 27 September 2020
• 7 µm lithography process
  ...y used by some semiconductor companies during the early to mid 1970s. This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes. |Process Name
  710 bytes (91 words) - 06:15, 18 January 2022
• 5 µm lithography process
  ...technology used by some semiconductor companies during the mid 1970s. This process was later superseded by [[3 µm]], [[2 µm]], and [[1.5 µm]] processes. ...on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the density and more than ten-folding t
  2 KB (325 words) - 06:22, 20 July 2018
• 3.5 µm lithography process
  ...ctive channel length of roughly 3.5 µm between the source and drain. This process was later superseded by [[3 µm]], [[2 µm]], and [[1.5 µm]] processes. |Process Name
  1 KB (122 words) - 06:21, 20 July 2018
• 2.5 µm lithography process
  ...by some semiconductor companies during the late 1970s to early 1980s. This process was later superseded by [[2 µm]], [[1.5 µm]], and [[1 µm]] processes. Harris Corporation operated a 2.5 μm CMOS process, '''SAJI IV''' (Self-Aligned) .
  563 bytes (64 words) - 06:20, 20 July 2018
• 750 nm lithography process
  ...m process]]. Commercial [[integrated circuit]] manufacturing using 750 nm process began in early 1990s. 750 nm and was phased out and later replaced by [[650 |Process Name
  1 KB (134 words) - 06:17, 20 July 2018
• 280 nm lithography process
  ...nm process]]. Commercial [[integrated circuit]] manufacturing using 280 nm process began in late 1990s. 280 nm and was phased out and later replaced by [[250 ....35 µm]] (this is why some Intel documents refer to it as "0.35µm"). The process was used in Intel's {{intel|P55C}} ({{x86|MMX}}) and {{intel|P6|l=arch}} {{
  2 KB (225 words) - 06:11, 20 July 2018
• 220 nm lithography process
  ...50 nm process]]. Commercial [[integrated circuit]] manufacturing using 220 process began in late 1990s. 220 nm and was phased out and later replaced by [[180 |Process Name
  975 bytes (117 words) - 06:10, 20 July 2018
• 240 nm lithography process
  ...50 nm process]]. Commercial [[integrated circuit]] manufacturing using 240 process began in late 1990s. 240 nm and was phased out and later replaced by [[220 |Process Name
  820 bytes (102 words) - 06:10, 20 July 2018
• 80 nm lithography process
  ...This technology superseded by commercial [[65 nm lithography process|65 nm process]] by 2006.
  1 KB (136 words) - 05:55, 20 July 2018
• microsystems international
  '''Microsystems International, LTD.''' ('''MIL''') was an early semiconductor manufacturing company. MIL manufactured [[wafers]], [[integrated circuits]] ...047709}}</ref>. Before folding, however, MIL did become one of the largest semiconductor companies in the world. In [[1975]] MIL ceased to operate (note that variou
  2 KB (289 words) - 07:23, 29 April 2016
• amd/am386
  ...le for the project was headed by Ben Oliver's group in their new [[0.8 µm process]] in [[wikipedia:Austin, TX|Austin, TX]]. Development took around eighteen ...st=Fletcher|first=Andrew|middle=E|year=2013|title=Profile of the Worldwide Semiconductor Industry - Market Prospects to 1997: Market Prospects to 1997|publisher=Els
  8 KB (1,077 words) - 14:50, 2 April 2020
• amd/am486
  ...st=Fletcher|first=Andrew|middle=E|year=2013|title=Profile of the Worldwide Semiconductor Industry - Market Prospects to 1997: Market Prospects to 1997|publisher=Els ...ng write-back and double the L1$ size which was manufactured on a [[350 nm process]].
  13 KB (1,897 words) - 09:30, 21 July 2021
• 700 nm lithography process
  ...m process]]. Commercial [[integrated circuit]] manufacturing using 700 nm process began in early 1990s. 700 nm and was phased out and later replaced by [[650 |Process Name
  928 bytes (114 words) - 06:17, 20 July 2018
• uc davis/kilocore
  | process = 32 nm ...(VCL)] at UC Davis. The chip, which was manufactured on [[IBM]]'s [[32 nm process]] PD-SOI technology, has a maximum computation rate of 1.78 trillion fully-
  8 KB (1,031 words) - 14:09, 10 May 2019
• 2016
  ...22: Intel phased out their {{intel|Tick-Tock}} model in favor of a {{intel|Process-Architecture-Optimization}} model. * April 28: [[Cypress Semiconductor]] acquires [[Broadcom]]'s Wireless Internet of Things Business for $550 mil
  5 KB (593 words) - 01:28, 5 August 2018
• 2014
  ..., 3rd generation {{intel|Xeon Phi}} which would be fabricated on a [[10 nm process]] * December 1: [[Fujitsu]] spins off [[300mm]] Mie fab as [[Mie Fujitsu Semiconductor]]
  635 bytes (80 words) - 16:32, 29 June 2018
• arm holdings/microarchitectures/cortex-a53
  |process=40 nm |process 2=28 nm
  6 KB (758 words) - 13:01, 6 March 2022
• 2017
  ...B investment in Fab 42 which will be used to manufacture chips on a [[7 nm process]] * March 28: Intel introduces their [[10 nm process]] featuring the highest density transistor at the time
  8 KB (999 words) - 11:04, 3 January 2019
• wafer size
  ...and is an important parameter as part of the [[semiconductor manufacturing process]]. A larger wafer size enables the fabrication of more [[dies]] per wafer w ...them. Unfortunately increasing the wafer size is far from being a trivial process - costing billions in [[research & development]]. The transition to 300 mm
  2 KB (283 words) - 19:42, 28 June 2019
• ibm
  ...ries]]. While they still design chips, they are now operating as a fabless semiconductor business.
  2 KB (251 words) - 11:14, 15 September 2019
• arm/history
  ...cessor, the {{armh|ARM1}}, was fabricated on [[VLSI Technology]]'s [[3 µm process]] using just 24,800 transistors. First silicon prototypes were delivered on ...processor. By the following year Acorn reimplemented the ARM1 on a smaller process along with a number of enhancements designed to address those precise probl
  6 KB (834 words) - 01:12, 29 January 2019
• 3 nm lithography process
  ...process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023. | process 1 fab = [[Intel]]
  5 KB (558 words) - 19:04, 29 December 2023
• fujitsu
  ...hich gave them 15.9% stake in MIFS in exchange for licensing their [[40 nm process]]. The remaining 84.1% stake in MIFS was eventually sold to [[UMC]] for 57.
  2 KB (185 words) - 16:26, 29 June 2018
• intel/process
  {{intel title|Process Technology History}} This article details '''[[Intel]]'s [[semiconductor process technology]]''' history for research and posterity.
  13 KB (1,998 words) - 03:56, 4 March 2022
• equivalent oxide thickness
  ...ature allowed for the industry to continue on with [[Moore's Law]]. As the semiconductor industry began to experiment with transitioning from a SiO₂ gate ...used by [[Intel]] following their transition to [[high-κ]] at the [[45 nm process]] node.
  2 KB (363 words) - 08:30, 29 April 2024
• arm holdings/microarchitectures/cortex-a55
  |process=16 nm |process 2=14 nm
  4 KB (603 words) - 04:23, 27 April 2023
• arm holdings/microarchitectures/cortex-a75
  |process=16 nm |process 2=14 nm
  2 KB (278 words) - 03:26, 6 May 2024
• dec
  '''Digital Equipment Corporation''' ('''DEC''') was a major American semiconductor corporation and a pioneer of minicomputers. * {{decc|Process Technology}}
  2 KB (196 words) - 19:33, 17 June 2017
• dec/microarchitectures/strongarm
  |process=0.35 µm ...er hand, which was design using DEC's own in-house tools and semiconductor process, resulted in performance increase of up to 5 times as much. StrongARM enjoy
  5 KB (738 words) - 13:49, 15 July 2018
• dec/process
  {{dec title|Process Technology History}} This article details details '''[[DEC]]'s [[semiconductor process technology]]''' history for research and posterity.
  4 KB (588 words) - 00:02, 26 December 2017
• arm holdings/microarchitectures/arm6
  |process=0.8 µm == Process Technology ==
  11 KB (1,679 words) - 18:49, 18 May 2023
• arm holdings/microarchitectures/arm7
  ...This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The ARM7 was the first majo * [[AMI Semiconductor]]
  3 KB (293 words) - 05:02, 31 December 2018
• mtr-mm²
  ...tor density]] unit that serves as a [[figure of merit]] in quantifying a [[process node]]. The metric makes use of a weighted system consisting of two typica ...me. The metric was formally proposed by Mark Bohr, [[Intel]]'s director of process architecture and integration, in 2017, although similar analysis have been
  4 KB (634 words) - 12:16, 25 April 2020
• semiconductor
  {{title|Semiconductor}}{{semi devices}} ...material whose [[conductivity]] characteristics can be varied. That is, a semiconductor is any material that can function as an [[insulator]] under certain conditi
  1 KB (173 words) - 23:30, 6 August 2018
• 2018
  * April: TSMC ramps its [[7nm#TSMC|7nm process]] * April 1: [[ON Semiconductor]] increased stake in [[Aizu Fujitsu Semiconductor]] to 40%
  5 KB (639 words) - 01:27, 30 December 2019
• cyrix/microarchitectures/joshua
  |process=0.180 µm ...e was an entirely [[Cyrix]] design when they were still part of [[National Semiconductor]]. The name was changed from Gobi to Joshua following the acquisition of Cy
  1 KB (145 words) - 23:09, 19 January 2018
• electronic-grade silicon
  '''Electronic-grade silicon''' ('''EGS''' or '''EG-Si''') or '''semiconductor-grade silicon''' ('''SGS''') is a highly-purified version of the [[metallur ...silicon with purity level as high as 9N or even 10N (99.99999999998%). The process results in TCS decomposing with the pure silicon being deposited on the hig
  3 KB (425 words) - 07:21, 4 December 2020
• through-silicon via
  ...king thru-connections in semiconductor wafers", more formally develops the process of producing through-silicon vias.
  976 bytes (129 words) - 20:04, 27 December 2022
• process shrink
  {{title|Process Shrink}} ...ess shrink''' (sometimes '''die shrink''') refers to the down-scaling of [[semiconductor devices]] through various means such as [[optical shrinks]] or standard cel
  285 bytes (34 words) - 06:46, 28 June 2018
• mifs
  {{title|Mie Fujitsu Semiconductor (MIFS)}} '''Mie Fujitsu Semiconductor''' ('''MIFS''') is a Japanese pure-play foundry, wholly-owned subsidiary of
  1 KB (182 words) - 16:25, 29 June 2018
• bkm
  ...rocedure that is considered the current standard on how to execute a given process. ...itionally, the term "Best Practice" is mistakenly understood as making the process definition immutable. People feel the "Best Practice" can't be published un
  1,022 bytes (152 words) - 12:56, 1 December 2019
• arm holdings/microarchitectures/neoverse n1
  |process=7 nm ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  |process=12 nm |process 2=7 nm
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  |process=10 nm |process 2=7 nm
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  |process=10 nm |process 2=7 nm
  21 KB (3,067 words) - 09:25, 31 March 2022
• arm holdings/microarchitectures/neoverse n2
  |process=7 nm ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  1 KB (166 words) - 00:04, 26 April 2021
• arm holdings/microarchitectures/poseidon
  |process=5 nm ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  1 KB (151 words) - 04:38, 29 August 2019
• intel/copy exactly!
  ...ancies, improve transfer time, and reduce risk when [[ramping up]] a new [[process technology]]. ...cations that could be applied in order to improve the process. Since then, process technologies have increased significantly in complexity. This meant those m
  3 KB (443 words) - 12:34, 26 December 2018
• arm holdings/microarchitectures/cortex-a72
  ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which imple * TSMC [[20 nm process]]
  2 KB (291 words) - 15:57, 4 July 2022
• arm holdings/microarchitectures/cortex-a57
  ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which imple <tr><th>Process</th><td>[[20 nm]]</td><td>[[16 nm]]</td></tr>
  4 KB (474 words) - 21:13, 25 April 2021
• arm holdings/microarchitectures/cortex-a15
  ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microa * [[28 nm process]] (from [[40 nm]])
  3 KB (347 words) - 14:40, 31 December 2018
• arm holdings/microarchitectures/cortex-a9
  |process=40 nm ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  2 KB (285 words) - 12:27, 28 July 2019
• arm holdings/microarchitectures/cortex-a8
  |process=65 nm |process 2=45 nm
  3 KB (428 words) - 14:30, 31 December 2018
• arm holdings/microarchitectures/cortex-a7
  |process=40 nm |process 2=28 nm
  2 KB (275 words) - 14:24, 31 December 2018
• arm holdings/microarchitectures/cortex-a12
  ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A12 was designed * [[28 nm process]] (from [[40 nm]])
  1 KB (167 words) - 14:25, 31 December 2018
• arm holdings/microarchitectures/cortex-a17
  ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A17 was designed * TSMC [[28 nm process]]
  2 KB (184 words) - 14:25, 31 December 2018
• arm holdings/microarchitectures/arm11
  ...This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The ARM11 was designed by t * [[Semiconductor]]
  2 KB (202 words) - 05:05, 31 December 2018
• arm holdings/microarchitectures/arm9
  ...This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. * [[Capital Semiconductor Ltd]]
  4 KB (391 words) - 03:45, 9 October 2020
• arm holdings/microarchitectures/arm8
  ...This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. * 2x performance (ARM810 vs ARM710 on the same [[process node]])
  1 KB (154 words) - 16:49, 15 October 2019
• arm holdings/microarchitectures/arm9/pr1
  ...extends the success of our extremely popular Thumb technology, giving our semiconductor partners and their customers the competitive advantage they need." The ARM9 architecture is available for licensing now. Designed to a process portable 0.35 micron rule-set, both processors can be implemented as an emb
  8 KB (1,261 words) - 22:05, 29 December 2018
• self-aligned contact
  '''Self-Aligned Contact''' ('''SAC''') is a semiconductor process flow technique that adds a protective [[dielectric]] layer over the [[trans ...d SAC along with the first high-volume [[FinFET]] process at their [[22 nm process node]]. Three new steps were introduced. The flow is as follow.
  4 KB (575 words) - 11:12, 13 October 2019
• yield
  ...on the yielding [[wafers]] that are not discarded during the manufacturing process. ...perate as desired within specs. Yield is a quantitative measurement of the process quality in terms of working dies.
  2 KB (352 words) - 13:53, 4 July 2019
• semiconductor manufacturing process
  {{title|Semiconductor Manufacturing Process}} ...he series of steps used to create [[integrated circuits]]. The fabrication process comprises a series of [[chemical]]- and [[lithography]]-related steps where
  1 KB (173 words) - 10:26, 1 February 2019
• deep trench capacitor
  Deep trench capacitors (DTCs) are vertical semiconductor devices that are used to add [[capacitance]] to various integrated circuits ...sed to generic [[DRAM]] ICs which relies on a special [[process technology|process]] not suitable for general logic).
  2 KB (312 words) - 08:46, 29 May 2020
• arm holdings/microarchitectures/mlp
  |process=16 nm |process 2=7 nm
  9 KB (1,379 words) - 22:35, 6 February 2020
• arm holdings/microarchitectures/cortex-m55
  |process=55 nm |process 2=45 nm
  12 KB (1,806 words) - 10:51, 12 January 2021
• multi-project wafer
  ...g dozens of [[masks]] with each costing in the millions for a leading-edge process. Designing prototype chips by small organizations, schools, and other entit
  1,021 bytes (143 words) - 17:35, 13 May 2020
• arm holdings/microarchitectures/cortex-x1
  |process=10 nm |process 2=7 nm
  7 KB (995 words) - 14:21, 4 July 2022
• arm holdings/microarchitectures/neoverse v1
  |process=7 nm ...chitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  5 KB (748 words) - 16:20, 4 July 2022
• arm holdings/microarchitectures/cortex-a510
  |process=7 nm |process 2=6 nm
  15 KB (2,282 words) - 11:20, 10 January 2023
• alchemy/au1200-333mgc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  6 KB (862 words) - 01:16, 19 March 2022
• contact over active gate
  ...act Over Active Gate''' ('''SA'''-'''COAG''') is an enhanced semiconductor process flow technique that removes the need for the gate contact to land at the en ...e is a flow extension that builds on top and extends previously-introduced process flow called [[self-aligned contacts]] (SAC). SAC is followed with an additi
  3 KB (354 words) - 23:31, 19 June 2022
• single diffusion break
  ...k''' ('''SDB''') or '''Single Dummy Gate''' ('''SDG''') is a semiconductor process flow technique that eliminates the need for an additional dummy gate paddin ...ing devices in order to provide good process control (stress) and reduce [[process variability|variations]]. Single diffusion break reduces the cell-to-cell s
  2 KB (294 words) - 18:24, 25 June 2022
• alchemy/au1000-266mcc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 266 MHz with a typ
  4 KB (607 words) - 00:41, 16 March 2022
• alchemy/au1000-266mci
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 266 MHz with a typ
  4 KB (614 words) - 00:45, 16 March 2022
• alchemy/au1000-400mcc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typ
  4 KB (594 words) - 00:47, 16 March 2022
• alchemy/au1000-500mcc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typ
  4 KB (594 words) - 00:50, 16 March 2022
• alchemy/au1500-333mbc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (562 words) - 01:07, 16 March 2022
• alchemy/au1500-333mbd
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (559 words) - 01:10, 16 March 2022
• alchemy/au1500-333mbf
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (566 words) - 01:12, 16 March 2022
• alchemy/au1500-333mbi
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (573 words) - 01:15, 16 March 2022
• alchemy/au1500-400mbc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typ
  4 KB (553 words) - 01:17, 16 March 2022
• alchemy/au1500-400mbd
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typ
  4 KB (546 words) - 01:20, 16 March 2022
• alchemy/au1500-500mbc
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typ
  4 KB (553 words) - 01:25, 16 March 2022
• alchemy/au1500-500mbd
  |process=180 nm ...[[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typ
  4 KB (546 words) - 01:29, 16 March 2022
• alchemy/au1100-333mbc
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (621 words) - 08:44, 17 March 2022
• alchemy/au1100-333mbd
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (624 words) - 08:46, 17 March 2022
• alchemy/au1100-333mbf
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (631 words) - 08:49, 17 March 2022
• alchemy/au1100-333mbi
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 333 MHz with a typ
  4 KB (632 words) - 08:51, 17 March 2022
• alchemy/au1100-400mbc
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typ
  4 KB (612 words) - 08:55, 17 March 2022
• alchemy/au1100-400mbd
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typ
  4 KB (611 words) - 08:58, 17 March 2022
• alchemy/au1100-500mbc
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typ
  4 KB (612 words) - 09:00, 17 March 2022
• alchemy/au1100-500mbd
  |process=130 nm ...by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typ
  4 KB (611 words) - 09:02, 17 March 2022
• alchemy/au1550-333mbc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  4 KB (613 words) - 09:17, 17 March 2022
• alchemy/au1550-333mbd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  4 KB (616 words) - 09:23, 17 March 2022
• alchemy/au1550-333mbf
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  4 KB (623 words) - 09:25, 17 March 2022
• alchemy/au1550-333mbi
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  4 KB (624 words) - 09:28, 17 March 2022
• alchemy/au1550-400mbc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  4 KB (604 words) - 09:30, 17 March 2022
• alchemy/au1550-400mbd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  4 KB (603 words) - 09:32, 17 March 2022
• alchemy/au1550-500mbc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  4 KB (604 words) - 09:33, 17 March 2022
• alchemy/au1550-500mbd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  4 KB (603 words) - 09:38, 17 March 2022
• alchemy/au1200-333mgd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  6 KB (865 words) - 01:18, 19 March 2022
• alchemy/au1200-333mgf
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  6 KB (872 words) - 01:19, 19 March 2022
• alchemy/au1200-333mgi
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  6 KB (873 words) - 01:23, 19 March 2022
• alchemy/au1200-400mgc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  6 KB (859 words) - 01:24, 19 March 2022
• alchemy/au1200-400mgd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  6 KB (858 words) - 01:26, 19 March 2022
• alchemy/au1200-500mgc
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  6 KB (853 words) - 01:27, 19 March 2022
• alchemy/au1200-500mgd
  |process= ...]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  6 KB (852 words) - 01:30, 19 March 2022
• alchemy/au1210-333mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  5 KB (645 words) - 01:47, 19 March 2022
• alchemy/au1210-333mgf
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 333 MH
  5 KB (652 words) - 01:50, 19 March 2022
• alchemy/au1210-400mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  5 KB (645 words) - 01:51, 19 March 2022
• alchemy/au1210-400mgf
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  5 KB (652 words) - 01:53, 19 March 2022
• alchemy/au1250-400mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  5 KB (661 words) - 01:55, 19 March 2022
• alchemy/au1250-400mgf
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MH
  5 KB (668 words) - 01:57, 19 March 2022
• alchemy/au1250-500mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  5 KB (661 words) - 01:58, 19 March 2022
• alchemy/au1250-500mgf
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 500 MH
  5 KB (668 words) - 01:59, 19 March 2022
• alchemy/au1250-600mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 600 MH
  5 KB (648 words) - 02:00, 19 March 2022
• alchemy/au1250-700mgd
  |process= ...gned by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 700 MH
  5 KB (641 words) - 02:05, 19 March 2022
• alchemy/microarchitectures/au1
  |process=180 nm |process 2=130 nm
  13 KB (2,114 words) - 16:00, 17 April 2022
• alchemy/alchemy
  ...mplementing the [[MIPS32]] ISA. They were originally designed by [[Alchemy Semiconductor]] and target communication and media devices, e.g. wireless gateways and ac ...was introduced on April 8, 2002. In February 2002 [[AMD]] acquired Alchemy Semiconductor in order to compete with [[Intel]]'s ARM-based [[XScale]] processors. AMD's
  31 KB (4,972 words) - 03:09, 20 March 2022