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Alchemy Au1000-500MCC
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Alchemy Au1000-500MCC
General Info
Model NumberAu1000-500MCC
Part NumberAu1000-500MCC
IntroductionJune 13, 2000 (announced)
February 2001 (launched)
General Specs
Frequency500 MHz
Core SteppingDA, HA, HB, HC, HD
Process180 nm
Word Size32 bit
Max Memory192 MiB
Max SMP1-Way (Uniprocessor)
Vcore1.8 V ± 5%
VI/O3.3 V
TDP (Typical)900 mW
Tcase0 °C – 85 °C
Tstorage-40 °C – 125 °C

Au1000-500MCC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 900 mW.


Main article: Au1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associativewrite-back

Memory controller[edit]

Au1000 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeSDR-133
Supports ECCNo
Max Mem192 MiB
Width32 bit
Max Bandwidth0.500 GB/s
0.287 GiB/s
294.253 MiB/s
2.806322e-4 TiB/s
3.086207e-4 TB/s


  • USB 1.1 (OHCI) host controller, USB 1.1 device controller
    • Two USB host ports and one device port
  • Two 10/100 Mbit/s Ethernet MAC controllers
  • Low speed interfaces AC97, I2S, Fast IrDA, 2 × SSI, 4 × UART, and up to 32 GPIOs


This processor has no integrated graphics processing unit.


  • 8-channel DMA engine
  • RTC and TOY timer
  • Two interrupt controllers
  • Power management unit
  • MIPS EJTAG interface
  • Idle Mode, Sleep Mode


  • 324-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
  • 22 × 22 grid, 1.0 mm pitch
  • 23 mm × 23 mm × 1.5 mm


Facts about "Alchemy Au1000-500MCC"
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core steppingDA +, HA +, HB +, HC + and HD +
core voltage1.8 V (18 dV, 180 cV, 1,800 mV) +
core voltage tolerance5% +
designerAlchemy +
familyAlchemy +
first announcedJune 13, 2000 +
first launchedFebruary 2001 +
full page namealchemy/au1000-500mcc +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaMIPS32 +
l1$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
ldateFebruary 2001 +
manufacturerTSMC +
market segmentEmbedded +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count1 +
max memory192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth0.287 GiB/s (0.5 GB/s, 294.253 MiB/s, 2.806322e-4 TiB/s, 3.086207e-4 TB/s) +
max memory channels1 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureAu1 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAu1000-500MCC +
nameAlchemy Au1000-500MCC +
part numberAu1000-500MCC +
process180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways1 +
supported memory typeSDR-133 +
tdp (typical)0.9 W (900 mW, 0.00121 hp, 9.0e-4 kW) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +