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Alchemy Au1000-500MCC
General Info
Designer	Alchemy
Manufacturer	TSMC
Model Number	Au1000-500MCC
Part Number	Au1000-500MCC
Market	Embedded
Introduction	June 13, 2000 (announced) February 2001 (launched)
General Specs
Family	Alchemy
Frequency	500 MHz
Microarchitecture
ISA	MIPS32
Microarchitecture	Au1
Core Stepping	DA, HA, HB, HC, HD
Process	180 nm
Technology	CMOS
Word Size	32 bit
Cores	1
Max Memory	192 MiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.8 V ± 5%
VI/O	3.3 V
TDP (Typical)	900 mW
Tcase	0 °C – 85 °C
Tstorage	-40 °C – 125 °C

Au1000-500MCC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 900 mW.

Cache

Main article: Au1 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1 × 16 KiB 4-way set associative write-back

Memory controller

Au1000 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type SDR-133 Supports ECC No Max Mem 192 MiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 0.500 GB/s 0.466 GiB/s 476.837 MiB/s 500 MB/s 4.547474e-4 TiB/s 5.0e-4 TB/s

Expansions

• USB 1.1 (OHCI) host controller, USB 1.1 device controller
  • Two USB host ports and one device port
• Two 10/100 Mbit/s Ethernet MAC controllers
• Low speed interfaces AC97, I2S, Fast IrDA, 2 × SSI, 4 × UART, and up to 32 GPIOs

Graphics

This processor has no integrated graphics processing unit.

Features

• 8-channel DMA engine
• RTC and TOY timer
• Two interrupt controllers
• Power management unit
• MIPS EJTAG interface
• Idle Mode, Sleep Mode

Package

• 324-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
• 22 × 22 grid, 1.0 mm pitch
• 23 mm × 23 mm × 1.5 mm

Bibliography

• "Product Brief: The Alchemy Au1000™ Internet Edge Processor", Alchemy, 2000
• "Product Brief: AMD Alchemy™ Solutions Au1000™ Processor Family Internet Edge Processor", AMD Publ. #26328, Rev. E, 2003
• "AMD Alchemy™ Au1000™ Processor Data Book", AMD Publ. #30360, Rev. D, September 2005
• "AMD Alchemy™ Au1000™ Processor Specification Update", AMD Publ. #27348, Rev. E, June 2005
• Hoeppner, Greg. "Au1000 Internet Edge Processor", Embedded Processor Forum 2000, June 13, 2000
• Plummer, Suzanne. "The Au1000™ Internet Edge Processor: A High Performance, Low Power SOC", Hot Chips 12, August 13, 2000
• Bassett, Paul. "Alchemy Au1x00", Hot Chips 14, August 19, 2002