Semiconductor & Computer Engineering
| Edit Values | |
| Neoverse V3 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2023 |
| Process | 5 nm, 4 nm |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 6 |
| Instructions | |
| ISA | ARMv9.0-A |
| Features | Poseidon |
| Cores | |
| Core Names | Neoverse (Voyager) |
| Succession | |
Neoverse V3 (Poseidon) is the successor to Neoverse V1 (Zeus), a high-performance ARM microarchitecture designed by ARM Holdings for the server market.
This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History[edit]
Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates[edit]
Poseidon is expected to show up in products around 2023.
- See also: Neoverse
Process Technology[edit]
Poseidon specifically designed takes advantage of the power and area advantages of the 5 nm process.
All Neoverse V1/V2/V3 Processors[edit]
| List of Neoverse V1/V2/V3-based Processors | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| Main processor | ISA | ||||||||
| Model | Part number | Family | Arch | Cores | Frequency | Process | Launched | ISA | Bits |
| AWS Graviton3 | ALC13B00 | Graviton | Neoverse V1 | 64 | 2.6 GHz 2,600 MHz 2,600,000 kHz | 5 nm 0.005 μm 5.0e-6 mm | 30 November 2021 | ARMv8.4-A | 64 bit 8 octets 16 nibbles |
| AWS Graviton4 | ALC14C00 | Graviton | Neoverse V2 | 96 | 2.8 GHz 2,800 MHz 2,800,000 kHz | 4 nm 0.004 μm 4.0e-6 mm | 28 November 2023 | ARMv9.0-A | 64 bit 8 octets 16 nibbles |
| Count: 2 | |||||||||
Architecture[edit]
The codename Poseidon was first used for the generation succeeding Zeus, now V1, and targeted for 2021 on a 5 nm node.
With codename Poseidon a successor for Neoverse V1 (Zeus) was first publicly mentioned on TechCon 2018.
- Actual introduction (used by third party chip designers in their products) was given in form
- of a rough target date of 2021. Its initial realization process is said to be 5 nm by TSMC.
Neoverse V3[edit]
Neoverse V3 (codename "Poseidon") was teased by Arm alongside the V2 and E2 announcements.
- It is targeted for systems including DDR5, PCIe Gen 6, and CXL 3.0
Key changes from Neoverse V1 (Zeus)[edit]
This list is incomplete; you can help by expanding it.
Neoverse V2[edit]
Neoverse V2 (codename "Demeter") is derived from the ARM Cortex-X3 and implements the ARMv9.0-A instruction set.
Key changes from Neoverse V1[edit]
- ARMv9.0-A instruction set (from ARMv8.4-A)
- 4 nm process (from 5 nm)
- BTB capacity: 12K entries
- TAGE predictor: 8-table
- Micro-op cache: 1536 entries (reduced for efficiency)
- Decode width: 6
- Rename / Dispatch width: 8
- ROB: 320 entry
- Execution ports: 15
- L2 cache: 1024-2048 KB per core
- CMN-700 mesh interconnect
- Up to 256 cores per die
- Up to 512 MB SLC
- Up to 4 TB/s bandwidth
Automobile solution[edit]
- Neoverse V3AE (Poseidon-AE), Neoverse VN (Poseidon-VN) [Auto]
- Neoverse CSS N3 (Pioneer), Neoverse CSS V3 (Voyager)
Models[edit]
- AWS Graviton3 • 64× Neoverse V1 (2021)
- AWS Graviton4 • 96× Neoverse V2 (2023)
- Google Axion • 72× Neoverse V2 (2023)
- NVIDIA Tegra Grace (T241) • 72× Neoverse V2 (2023)
- NVIDIA Tegra Thor (T264) • Neoverse V3AE (2024)
Bibliography[edit]
- Drew Henry keynote, TechCon 2018 keynote.
| codename | Neoverse V3 + |
| designer | ARM Holdings + |
| first launched | 2023 + |
| full page name | arm holdings/microarchitectures/poseidon + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv9.0-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Neoverse V3 + |
| process | 5 nm (0.005 μm, 5.0e-6 mm) + and 4 nm (0.004 μm, 4.0e-6 mm) + |