|Graviton4 Package Front
|November 28, 2023 (announced)
November 28, 2023 (launched)
|Yes (7 dies)
AWS Graviton4 (Alpine ALC14C00) is a hexanonaconta-core ARMv9 multiprocessor designed by Amazon (Annapurna Labs) for Amazon's own infrastructure. Graviton4 is a 5 nm(?) 7-chiplet design SoC based on the Arm CMN-700 mesh interconnect and Neoverse V2 core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory along with 96 lanes of PCIe 5.0.
This 4th-generation server processor was first announced during Amazon's AWS re:Invent 2023 by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center occurred in early 2024. These processors are offered as part of Amazon's EC2 instances.
Graviton4 features a 7-chiplet design similar to its predecessor, Graviton3. This chip features 96 cores, 50% more than the prior generation. The core implementation was updated to Arm's Neoverse V2 microarchitecture with 2x256b SVE support, also bringing support up to Armv9.0 ISA for the first time. The chip supports up to 12 channels for DDR5 ECC DIMMs with data rates of up to 5600 MT/s. The Graviton4 tripled the number of PCIe lanes to 96 lanes of PCIe 5.0.
The Graviton4 is the first chip from the Graviton family to feature multiprocessing support. The chip introduced dual-socket support with full coherency for up to 192 vCPUs and DDR5 channels on a single server. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be configured to run in a number of modes that can potentially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system.
The Graviton4 features a 7-chiplet architecture similar in design to the Graviton3. The compute SoC die sits in the middle with 4 DDR memory controller dies and 2 PCIe controller dies. Each DDR memory controller features support for 3 memory channels - two dies to the east and two dies to the west for a total of 6 memory channels on each side. There are two PCIe controller dies - one to the north and one to the south of the chip. The four DDR memory controller dies are interconnected with the SoC via embedded silicon bridges in the package.Unlike the Graviton3, the two PCIe controller dies are not abutting the compute SoC die and are no longer controller via an embedded bridge in the package.
- Main article: Neoverse V2 § Cache