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Alchemy Au1100-400MBD
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Alchemy Au1100-400MBD
General Info
DesignerAlchemy
ManufacturerTSMC
Model NumberAu1100-400MBD
Part NumberAu1100-400MBDBA,
Au1100-400MBDBC,
Au1100-400MBDBD,
Au1100-400MBDBE,
Au1100-400MBDBF
MarketEmbedded
IntroductionApril 8, 2002 (launched)
Release Price$29.50 (tray)
General Specs
FamilyAlchemy
Frequency400 MHz
Microarchitecture
ISAMIPS32
MicroarchitectureAu1
Core SteppingBA, BC, BD, BE, BF
Process130 nm
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory192 MiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.22 V
VI/O3.3 V
TDP (Typical)250 mW
Tcase0 °C – 70 °C
Tstorage-40 °C – 125 °C

Au1100-400MBD was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 130 nm process, this SoC operates at a base frequency of up to 400 MHz with a typical TDP of 250 mW. It is the Pb-free version of the Au1100-400MBC.

Cache[edit]

Main article: Au1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associativewrite-back

Memory controller[edit]

Au1100 processors integrate two independent memory controllers, a DRAM controller which supports 2.5 V / 3.3 V SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeSDR-133
Supports ECCNo
Max Mem192 MiB
Controllers1
Channels1
Width32 bit
Max Bandwidth0.400 GB/s
0.23 GiB/s
235.402 MiB/s
2.245057e-4 TiB/s
2.468966e-4 TB/s

Expansions[edit]

  • USB 1.1 (OHCI) host controller, USB 1.1 device controller
    • Two USB host ports and one device port
  • One 10/100 Mbit/s Ethernet MAC controller
  • Two Secure Digital/SDIO 1.1 controllers
  • Low speed interfaces AC97, I2S, Fast IrDA, 2 × SSI, 3 × UART, and up to 48 GPIOs

Graphics[edit]

Au1100 processors integrate an LCD controller which supports panels with a resolution up to 800 × 600 pixels.

  • TFT: 1/2/4/8-bit mono, 12/16-bit color (4:4:4/5:6:5 RGB)
  • STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
  • Frame buffer formats:
    • 1/2/4/8-bpp palettized
    • 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1 RGBI
  • Double buffering
  • Hardware swivel (90, 180, 270 degrees) for up to 320 × 240 pixel displays
  • Two PWM clocks to control contrast and brightness voltages

Features[edit]

  • 8-channel DMA engine
  • RTC and TOY timer
  • Two interrupt controllers
  • Power management unit
  • MIPS EJTAG interface
  • Idle Mode, Sleep Mode

Package[edit]

  • 399-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
  • 20 × 20 grid, 0.8 mm pitch
  • 17 mm × 17 mm × 1.7 mm

Bibliography[edit]

Facts about "Alchemy Au1100-400MBD"
base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core steppingBA +, BC +, BD +, BE + and BF +
core voltage1.22 V (12.2 dV, 122 cV, 1,220 mV) +
designerAlchemy +
familyAlchemy +
first launchedApril 8, 2002 +
full page namealchemy/au1100-400mbd +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaMIPS32 +
l1$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
ldateApril 8, 2002 +
manufacturerTSMC +
market segmentEmbedded +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count1 +
max memory192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth0.23 GiB/s (0.4 GB/s, 235.402 MiB/s, 2.245057e-4 TiB/s, 2.468966e-4 TB/s) +
max memory channels1 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureAu1 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAu1100-400MBD +
nameAlchemy Au1100-400MBD +
part numberAu1100-400MBDBA +, Au1100-400MBDBC +, Au1100-400MBDBD +, Au1100-400MBDBE + and Au1100-400MBDBF +
process130 nm (0.13 μm, 1.3e-4 mm) +
release price$ 29.50 (€ 26.55, £ 23.90, ¥ 3,048.24) +
release price (tray)$ 29.50 (€ 26.55, £ 23.90, ¥ 3,048.24) +
smp max ways1 +
supported memory typeSDR-133 +
tdp (typical)0.25 W (250 mW, 3.3525e-4 hp, 2.5e-4 kW) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +