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Alchemy Au1210-400MGD
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Alchemy Au1210-400MGD
General Info
Model NumberAu1210-400MGD
Part NumberAu1210-400MGD
IntroductionJanuary 9, 2007 (announced)
June 5, 2007 (launched)
General Specs
Frequency400 MHz
Word Size32 bit
Max Memory512 MiB
Max SMP1-Way (Uniprocessor)
Vcore1.0 V ± 10%
VI/O3.3 V
TDP1000 mW
TDP (Typical)420 mW
Tcase0 °C – 70 °C
Tstorage-40 °C – 125 °C

Au1210-400MGD was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by RMI based on earlier AMD and Alchemy Semiconductor processors this SoC operates at a base frequency of up to 400 MHz with a typical TDP of 420 mW and maximum TDP of 1000 mW. It was also available with an industrial temperature range as Au1210-400MGF.


Main article: Au1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associativewrite-back

Memory controller[edit]

Au1210 processors integrate two independent memory controllers, a DRAM controller which supports 2.5 V DDR and 1.8 V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, IDE PIO mode, and other I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. The integrated LCD and MAE peripherals can access the SDRAM controller through a 64-bit side bus running at the SBUS frequency.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR-400, DDR2-533
Supports ECCNo
Max Mem512 MiB
Width16 bit, 32 bit
Max Bandwidth1.600 GB/s
0.92 GiB/s
941.609 MiB/s
8.98023e-4 TiB/s
9.875862e-4 TB/s


  • USB 2.0 (EHCI) and 1.1 (OHCI) host controller, USB 2.0 device controller with OTG support
    • One USB host port and one host/device port, each low/fast/high speed capable
  • Two Secure Digital/SDHC/SDIO/MMC 1.1 controllers
  • Two Programmable Serial Controllers supporting the AC97, I2S, SPI, and SMBus protocols
  • Two UARTs
  • Up to 48 GPIOs


This processor integrates an LCD controller for panels with a resolution up to 2048 × 2048 pixels.

  • TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  • STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
  • Frame buffer formats:
    • 1/2/4/8-bpp pass through/grayscale/palettized
    • 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0
    • 24-bpp 8:8:8:0
    • 32-bpp 8:8:8:8 RGBA
  • Four overlay windows with double buffering
  • Gamma correction, alpha blending, and chroma keying
  • 32 × 32 × 2 bpp hardware cursor


  • Camera Interface Module (CIM)
    • ITU-R BT.656 compatible 8/9/10-bit bus running at up to 33 MHz
    • Support for UYVY and Bayer RGB to planar format conversion
  • Media Acceleration Engine (MAE) to accelerate video decoding in hardware
    • Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1
    • Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters
    • Hardware colorspace conversion and scaling with 4-tap filter, also for CIM
    • Video decode resolution up to Wide-CIF 480 × 288
  • 16-channel descriptor-based DMA controller
    • Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
    • 36-bit source and destination addresses with no alignment requirement
    • Scatter/gather and stride transfers
    • Compare and branch descriptors
  • RTC and TOY timer
  • Two interrupt controllers
  • Power management unit
  • MIPS EJTAG interface
  • Idle, Sleep, Hibernate Mode


  • 372-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
  • 23 × 23 grid, 0.8 mm pitch
  • 19 mm × 19 mm × 1.4 mm


Facts about "Alchemy Au1210-400MGD"
base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
core voltage tolerance10% +
designerRMI +
familyAlchemy +
first announcedJanuary 9, 2007 +
first launchedJune 5, 2007 +
full page namealchemy/au1210-400mgd +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaMIPS32 +
l1$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
ldateJune 5, 2007 +
market segmentEmbedded +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count1 +
max memory512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB, 4.882812e-4 TiB) +
max memory bandwidth0.92 GiB/s (1.6 GB/s, 941.609 MiB/s, 8.98023e-4 TiB/s, 9.875862e-4 TB/s) +
max memory channels1 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureAu1 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAu1210-400MGD +
nameAlchemy Au1210-400MGD +
part numberAu1210-400MGD +
smp max ways1 +
supported memory typeDDR-400 + and DDR2-533 +
tdp1 W (1,000 mW, 0.00134 hp, 0.001 kW) +
tdp (typical)0.42 W (420 mW, 5.6322e-4 hp, 4.2e-4 kW) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +