From WikiChip
Alchemy Au1500-500MBC
< alchemy

Edit Values
Alchemy Au1500-500MBC
General Info
DesignerAlchemy
ManufacturerTSMC
Model NumberAu1500-500MBC
Part NumberAu1500-500MBC
MarketEmbedded
IntroductionJune 11, 2001 (announced)
December 2001 (launched)
General Specs
FamilyAlchemy
Frequency500 MHz
Microarchitecture
ISAMIPS32
MicroarchitectureAu1
Core SteppingAB, AC, AD
Process180 nm
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory192 MiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.8 V ± 5%
VI/O3.3 V
TDP (Typical)1200 mW
Tcase0 °C – 70 °C
Tstorage-40 °C – 125 °C

Au1500-500MBC was a 32-bit ultra low power embedded microprocessor with an Au1 CPU core implementing the MIPS32 ISA. Designed by Alchemy Semiconductor and fabricated on a TSMC 180 nm LV process, this SoC operates at a base frequency of up to 500 MHz with a typical TDP of 1200 mW. It was also available as a Pb-free version Au1500-500MBD.

Cache[edit]

Main article: Au1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1 × 16 KiB4-way set associativewrite-back

Memory controller[edit]

Au1500 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, SMROM, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeSDR-133
Supports ECCNo
Max Mem192 MiB
Controllers1
Channels1
Width32 bit
Max Bandwidth0.500 GB/s
0.287 GiB/s
294.253 MiB/s
2.806322e-4 TiB/s
3.086207e-4 TB/s

Expansions[edit]

  • PCI 2.2 controller, 32-bit bus, 33 or 66 MHz
  • USB 1.1 (OHCI) host controller, USB 1.1 device controller
    • Two USB host ports and one device port
  • Two 10/100 Mbit/s Ethernet MAC controllers
  • Low speed interfaces AC97, 2 × UART, and up to 39 GPIOs

Graphics[edit]

This processor has no integrated graphics processing unit.

Features[edit]

  • 8-channel DMA engine
  • RTC and TOY timer
  • Two interrupt controllers
  • Power management unit
  • MIPS EJTAG interface
  • Idle Mode, Sleep Mode

Package[edit]

  • 424-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
  • 23 × 23 grid, 0.8 mm pitch, solder ball ⌀ 0.4 mm, 63Sn/37Pb
  • 19 mm × 19 mm × 1.45 mm

Bibliography[edit]

Facts about "Alchemy Au1500-500MBC"
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core steppingAB +, AC + and AD +
core voltage1.8 V (18 dV, 180 cV, 1,800 mV) +
core voltage tolerance5% +
designerAlchemy +
familyAlchemy +
first announcedJune 11, 2001 +
first launchedDecember 2001 +
full page namealchemy/au1500-500mbc +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaMIPS32 +
l1$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
ldateDecember 2001 +
manufacturerTSMC +
market segmentEmbedded +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count1 +
max memory192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth0.287 GiB/s (0.5 GB/s, 294.253 MiB/s, 2.806322e-4 TiB/s, 3.086207e-4 TB/s) +
max memory channels1 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureAu1 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAu1500-500MBC +
nameAlchemy Au1500-500MBC +
part numberAu1500-500MBC +
process180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways1 +
supported memory typeSDR-133 +
tdp (typical)1.2 W (1,200 mW, 0.00161 hp, 0.0012 kW) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +