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  • * ARM Holdings
    6 KB (711 words) - 17:01, 26 March 2019
  • {{title|ARM Holdings}} | name = Arm Holdings
    6 KB (733 words) - 22:02, 3 November 2022
  • | developer 2 = Arm Holdings | arch = Multicore 64-bit ARM SoCs
    7 KB (902 words) - 16:33, 12 January 2023
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (669 words) - 14:35, 5 August 2020
  • | designer 2 = ARM Holdings | isa family = ARM
    6 KB (647 words) - 09:57, 12 January 2018
  • | designer 2 = ARM Holdings | isa family = ARM
    6 KB (670 words) - 09:36, 22 August 2018
  • |designer=ARM Holdings ...performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/per
    6 KB (758 words) - 13:01, 6 March 2022
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (235 words) - 15:00, 15 February 2019
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a53]]
    56 bytes (5 words) - 03:45, 4 December 2016
  • |designer 2=ARM Holdings |isa family=ARM
    6 KB (713 words) - 21:16, 2 May 2021
  • | designer 2 = ARM Holdings | isa family = ARM
    6 KB (617 words) - 02:35, 14 December 2019
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (581 words) - 14:25, 12 September 2019
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (574 words) - 04:36, 23 June 2019
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (600 words) - 08:55, 12 October 2023
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (549 words) - 16:22, 29 December 2018
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (696 words) - 17:41, 15 August 2020
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (614 words) - 09:40, 12 February 2020
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (552 words) - 23:18, 3 November 2019
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (473 words) - 04:40, 23 June 2019
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (564 words) - 06:22, 30 March 2021
  • | developer 2 = ARM Holdings | arch = ARM performance processors
    10 KB (1,247 words) - 00:25, 8 November 2023
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (533 words) - 21:28, 27 March 2018
  • | designer 2 = ARM Holdings | isa family = ARM
    4 KB (386 words) - 04:42, 7 April 2022
  • | designer 2 = ARM Holdings | isa family = ARM
    3 KB (309 words) - 15:24, 5 September 2018
  • | designer = ARM Holdings | isa family = ARM
    4 KB (473 words) - 09:26, 3 December 2019
  • |designer=ARM Holdings ...to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embed
    4 KB (603 words) - 04:23, 27 April 2023
  • |designer=ARM Holdings ...be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a numb
    2 KB (278 words) - 03:26, 6 May 2024
  • == [[ARM Holdings]]== * {{armh|Cortex-A72|l=arch}}
    6 KB (914 words) - 11:36, 4 June 2020
  • | developer 2 = ARM Holdings '''R-Car''' is a family of embedded high-end [[ARM]]/[[SuperH]] [[system-on-chips]] for the automotive industry.
    6 KB (708 words) - 14:35, 24 March 2019
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (467 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (415 words) - 16:32, 13 December 2017
  • {{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
    2 KB (299 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (337 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (248 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (420 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (409 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (409 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (346 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (365 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (383 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (571 words) - 15:43, 29 December 2018
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (495 words) - 16:32, 13 December 2017
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (467 words) - 04:41, 21 July 2018
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (334 words) - 16:13, 13 December 2017
  • | developer 2 = ARM Holdings | arch = Performance mobile ARM SOCs
    3 KB (316 words) - 06:18, 3 October 2023
  • |designer 2=ARM Holdings |isa family=ARM
    6 KB (824 words) - 17:25, 1 January 2022
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (534 words) - 05:37, 26 May 2023
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (307 words) - 06:55, 26 June 2019
  • * February 5: [[Ampere Computing]] announces their first ARM processor, the {{ampere|A1}}. * February 13: [[ARM Holdings|ARM]] announces two new [[neural processors]] IPs - the {{armh|ML processor}} f
    5 KB (639 words) - 01:27, 30 December 2019
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (622 words) - 10:43, 7 March 2024
  • ...gs|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
    12 KB (1,869 words) - 10:01, 27 February 2019
  • ...gs|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
    7 KB (943 words) - 09:59, 27 February 2019
  • ...gs|ARM]] || {{armh|Cortex-A15|l=arch}} || rowspan="4" | [https://developer.arm.com/support/security-update Post] | {{armh|Cortex-A72|l=arch}}
    5 KB (649 words) - 21:16, 8 October 2018
  • |isa family=ARM | designer = ARM Holdings
    6 KB (800 words) - 05:21, 25 January 2022
  • ...provides cache coherency and management between the generic [[ARM Holdings|ARM]] {{armh|Cortex-A53|l=arch}} core cluster and Samsung's custom high-perform
    563 bytes (71 words) - 01:43, 5 February 2018
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (713 words) - 10:41, 7 March 2024
  • |designer 2=ARM Holdings |isa family=ARM
    443 bytes (55 words) - 22:19, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    449 bytes (55 words) - 00:11, 28 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    457 bytes (54 words) - 00:12, 28 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    439 bytes (55 words) - 08:43, 2 August 2018
  • |designer 2=ARM Holdings |isa family=ARM
    455 bytes (55 words) - 23:53, 28 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    558 bytes (65 words) - 23:56, 28 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    514 bytes (61 words) - 00:17, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    526 bytes (62 words) - 00:01, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    524 bytes (62 words) - 23:56, 28 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    514 bytes (62 words) - 00:23, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (507 words) - 13:08, 6 March 2022
  • |designer 2=ARM Holdings |isa family=ARM
    531 bytes (64 words) - 00:51, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    505 bytes (63 words) - 00:56, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    441 bytes (55 words) - 01:11, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    467 bytes (55 words) - 01:20, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    656 bytes (77 words) - 11:25, 15 February 2020
  • |designer 2=ARM Holdings |isa family=ARM
    478 bytes (56 words) - 01:52, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    443 bytes (55 words) - 02:01, 29 March 2018
  • |designer 2=ARM Holdings |isa family=ARM
    624 bytes (76 words) - 11:06, 16 January 2021
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (414 words) - 08:08, 29 June 2022
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (600 words) - 22:53, 9 December 2022
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (610 words) - 11:04, 5 July 2020
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (521 words) - 02:20, 16 February 2023
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:01, 12 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a55]]
    56 bytes (5 words) - 11:03, 25 May 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:01, 12 September 2018
  • | developer 2 = ARM Holdings ...dragon 7 Series Mobile Platforms''' is a family of mid-range {{arch|64}} [[ARM]] SoCs designed primarily for the upper mid-range mainstream smartphone mar
    3 KB (366 words) - 05:51, 3 October 2022
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (535 words) - 07:01, 10 September 2021
  • ...ucts in the future. The chip itself incorporates a dedicate [[ARM Holdings|ARM]] {{armh|Cortex-A53|l=arch}} core which handles the application-level resou
    4 KB (617 words) - 10:03, 19 April 2019
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (607 words) - 11:37, 19 April 2024
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:01, 12 September 2018
  • |designer 2=ARM Holdings |isa=ARM
    3 KB (340 words) - 16:24, 25 November 2020
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (359 words) - 00:19, 14 March 2023
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (320 words) - 04:44, 18 August 2021
  • | developer 2 = ARM Holdings | isa = ARM
    5 KB (656 words) - 05:07, 13 October 2019
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (273 words) - 03:03, 17 July 2019
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (282 words) - 20:49, 5 May 2019
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (355 words) - 10:12, 8 May 2019
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (445 words) - 02:43, 8 May 2019
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:00, 12 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:00, 12 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:01, 12 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:00, 12 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 17:01, 12 September 2018
  • |designer=ARM Holdings ...''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesiza
    7 KB (980 words) - 13:46, 18 February 2023
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a76]]
    56 bytes (5 words) - 17:49, 8 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a76]]
    56 bytes (5 words) - 17:50, 8 September 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a76]]
    56 bytes (5 words) - 17:50, 8 September 2018
  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a75
    14 KB (2,183 words) - 17:15, 17 October 2020
  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a76
    17 KB (2,555 words) - 06:08, 16 June 2023
  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a77
    21 KB (3,067 words) - 09:25, 31 March 2022
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 16:58, 12 September 2018
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (540 words) - 04:06, 18 December 2021
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (427 words) - 13:00, 23 August 2022
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (597 words) - 20:19, 16 January 2022
  • '''Kryo''' is a series of semi-custom [[ARM]] cores from [[ARM Holdings|Arm]] integrated by [[Qualcomm]] in their {{qualcomm|Snapdragon}} SoCs. ...are not Qualcomm's own design but rather a semi-custom implementation of [[Arm]]'s own {{armh|Cortex}} cores.
    3 KB (404 words) - 06:14, 15 March 2023
  • |designer 2=ARM Holdings |isa family=ARM
    9 KB (1,235 words) - 12:57, 16 December 2023
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (697 words) - 09:43, 28 April 2021
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 16:43, 13 December 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 16:43, 13 December 2018
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (359 words) - 06:15, 21 October 2022
  • |designer=ARM Holdings
    374 bytes (43 words) - 13:52, 29 December 2018
  • ...usiness. In other words, the Neoverse incorporates the technologies of the Arm ecosystem that spans from the [[edge]] to the [[cloud]]. ...neoverse announcement.jpg|thumb|right|Drew Henry Neoverse announcement at Arm TechCon 2018.]]
    2 KB (221 words) - 22:55, 25 April 2021
  • ...as top-of-rack switches, routers, and servers. The term was announced by [[Arm]] at TechCon 2018 when they introduced the {{\\|Neoverse}} in order to grou [[category:arm holdings]]
    561 bytes (82 words) - 20:37, 10 December 2019
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a53]]
    56 bytes (5 words) - 12:25, 25 December 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a53]]
    56 bytes (5 words) - 12:25, 25 December 2018
  • |designer=ARM Holdings |predecessor=Cortex-A72
    2 KB (205 words) - 23:49, 4 April 2021
  • {{armh title|Cortex-A72|arch}} |name=Cortex-A72
    2 KB (291 words) - 15:57, 4 July 2022
  • |designer=ARM Holdings |successor=Cortex-A72
    4 KB (474 words) - 21:13, 25 April 2021
  • |designer=ARM Holdings ...low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    3 KB (347 words) - 14:40, 31 December 2018
  • |designer=ARM Holdings ...}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    2 KB (285 words) - 12:27, 28 July 2019
  • |designer=ARM Holdings ...es to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.
    3 KB (428 words) - 14:30, 31 December 2018
  • |designer=ARM Holdings ...=arch}}, a high efficiency [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    2 KB (275 words) - 14:24, 31 December 2018
  • |designer=ARM Holdings ...}, a mid-range performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    1 KB (167 words) - 14:25, 31 December 2018
  • |designer=ARM Holdings ...}, a mid-range performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    2 KB (184 words) - 14:25, 31 December 2018
  • |designer=ARM Holdings ...arch}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    1 KB (159 words) - 14:25, 31 December 2018
  • |designer=ARM Holdings ...arch}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    839 bytes (98 words) - 00:00, 23 September 2019
  • |designer=ARM Holdings ...-A35}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    787 bytes (98 words) - 18:48, 7 April 2020
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (358 words) - 13:44, 29 December 2018
  • |designer=ARM Holdings ...panies to be implemented in their own chips. The ARM11 was designed by the Arm Sophia-Antipolis design center.
    2 KB (202 words) - 05:05, 31 December 2018
  • {{armh title|Cortex}}[[File:arm cortex logo.svg|thumb|right|class=wikichip_ogimage|Logo]] ...various edge market such as embedded and mobile. The Cortex family succeed Arm's {{\\|classic}} cores with more specialized cores with highly targeted req
    3 KB (404 words) - 01:01, 5 September 2022
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a9]]
    55 bytes (5 words) - 02:31, 31 December 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a8]]
    55 bytes (5 words) - 02:57, 31 December 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a8]]
    55 bytes (5 words) - 02:57, 31 December 2018
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a8]]
    55 bytes (5 words) - 02:57, 31 December 2018
  • '''Classic processors''' refer to [[Arm]]'s older series of processors, predating the modern {{\\|Cortex}} family. * ARM's {{arm|History}}
    349 bytes (49 words) - 15:06, 31 December 2018
  • | developer 2 = ARM Holdings | isa = ARM
    2 KB (225 words) - 10:59, 4 January 2019
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (253 words) - 13:26, 30 May 2020
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a75]]
    56 bytes (5 words) - 10:32, 13 January 2019
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (235 words) - 22:49, 8 November 2023
  • |designer 2=ARM Holdings |isa family=ARM
    4 KB (474 words) - 22:34, 13 September 2020
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (633 words) - 23:12, 15 July 2023
  • |designer 2=ARM Holdings |isa family=ARM
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  • #REDIRECT [[arm holdings/microarchitectures/cortex-a76]]
    56 bytes (5 words) - 20:59, 26 May 2019
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a76]]
    56 bytes (5 words) - 20:59, 26 May 2019
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a77]]
    56 bytes (5 words) - 23:59, 26 May 2019
  • |designer 2=ARM Holdings |isa family=ARM
    7 KB (943 words) - 15:22, 17 June 2023
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (441 words) - 23:23, 24 October 2021
  • |designer 2=ARM Holdings |isa family=ARM
    3 KB (366 words) - 04:55, 26 July 2021
  • |designer 2=ARM Holdings |isa family=ARM
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  • |designer=ARM Holdings ...-A35}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesiza
    1 KB (179 words) - 03:34, 4 December 2021
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (676 words) - 14:42, 16 March 2023
  • |designer 2=ARM Holdings |isa family=ARM
    5 KB (660 words) - 06:32, 26 May 2022
  • |designer 2=ARM Holdings |isa family=ARM
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  • |designer 2=ARM Holdings |isa family=ARM
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  • |designer 2=Arm Holdings |isa family=ARM
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  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a78
    728 bytes (80 words) - 13:49, 4 July 2022
  • |designer 2=ARM Holdings |isa family=ARM
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  • |designer 2=ARM Holdings |isa family=ARM
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  • #REDIRECT [[arm holdings/microarchitectures/cortex-a77]]
    56 bytes (5 words) - 15:43, 29 December 2019
  • |designer 2=ARM Holdings |isa family=ARM
    7 KB (1,043 words) - 09:30, 23 December 2022
  • | developer 2 = Arm Holdings | arch = Multicore 64-bit ARM SoCs
    2 KB (264 words) - 16:58, 3 February 2020
  • |isa family=ARM '''Dimensity 1000''' is a high-performance mobile [[ARM]] [[5G]] [[SoC]] designed by MediaTek serving as the company's 2020 flagshi
    4 KB (443 words) - 06:23, 3 July 2020
  • |isa family=ARM '''Dimensity 1000L''' is a high-performance mobile [[5G]] [[ARM]] [[SoC]] designed by MediaTek serving as the company's 2020 flagship proce
    3 KB (409 words) - 00:21, 1 June 2020
  • |designer=Arm Holdings ...is a first-generation [[neural processor]] microarchitecture designed by [[Arm]] for embedded and mobile SoCs as part of {{armh|Project Trillium}}. This m
    9 KB (1,379 words) - 22:35, 6 February 2020
  • |isa family=ARM '''Dimensity 800''' is a mid-range mobile [[ARM]] [[5G]] [[SoC]] designed by MediaTek launched in 2020. The Dimensity 800 i
    3 KB (367 words) - 21:17, 30 January 2021
  • |designer 2=ARM Holdings |isa family=ARM
    2 KB (301 words) - 22:02, 3 February 2020
  • |image=arm ethos.svg |developer=Arm Holdings
    4 KB (557 words) - 23:45, 10 February 2020
  • |designer=ARM Holdings ...be implemented in their own chips. The Cortex-M55, which implements the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microco
    12 KB (1,806 words) - 10:51, 12 January 2021
  • |designer=ARM Holdings |successor link=arm holdings/microarchitectures/cortex-x2
    7 KB (995 words) - 14:21, 4 July 2022
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a78]]
    56 bytes (5 words) - 09:43, 26 May 2020
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a77]]
    56 bytes (5 words) - 22:46, 6 June 2020
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a77]]
    56 bytes (5 words) - 22:46, 6 June 2020
  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a710
    625 bytes (70 words) - 13:51, 4 July 2022
  • |designer=ARM Holdings ...to the {{armh|Cortex-A55|l=arch}}. The Cortex-A510, which implements the {{arm|ARMv9.0}} ISA, is typically found in smartphone and other embedded devices.
    15 KB (2,282 words) - 11:20, 10 January 2023
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a510]]
    57 bytes (5 words) - 13:10, 21 August 2021
  • #REDIRECT [[arm holdings/microarchitectures/cortex-a510]]
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  • #REDIRECT [[arm holdings/microarchitectures/cortex-a710]]
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  • #REDIRECT [[arm holdings/microarchitectures/cortex-a715]]
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  • |designer=ARM Holdings ...lanned ultra-high efficiency [[microarchitecture]] being designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A510|l=arch}}. Hayes is scheduled for
    517 bytes (59 words) - 14:08, 4 July 2022
  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-a715
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  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-x1
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  • |designer=ARM Holdings |predecessor link=arm holdings/microarchitectures/cortex-x3
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