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R-Car H3 (SiP) - Renesas
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R-Car H3 (SiP)
r-car h3 (sip).png
General Info
DesignerRenesas, ARM Holdings
ManufacturerTSMC
Model NumberH3 (SiP)
Part NumberR8J77950
MarketEmbedded
IntroductionDecember 2, 2015 (announced)
March, 2018 (launched)
General Specs
FamilyR-Car
Series3rd Gen
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53, Cortex-A57, Cortex-R7
Core NameCortex-A53, Cortex-A57, Cortex-R7
Process16 nm
TechnologyCMOS
Die111.36 mm²
12.94 mm × 8.61 mm
Word Size64 bit
Cores9
Threads9
Max CPUs1 (Uniprocessor)
Electrical
Vcore0.8 V
VI/O3.3 V
Packaging
PackageFCBGA-1255 (BGA)
Dimension42.5 mm x 42.5 mm
Pitch0.80 mm
Ball Count1255
InterconnectBGA-1255

R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a dual-core lock-step Cortex-R7 for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.

This model is an SiP variant of the H3 which include the DDR memory on-package.

Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
0.625 MiB
655,360 B
6.103516e-4 GiB
L1I$352 KiB
0.344 MiB
360,448 B
3.356934e-4 GiB
4x48+5x32 KiB  
L1D$288 KiB
0.281 MiB
294,912 B
2.746582e-4 GiB
9x32 KiB  

L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-3200
Supports ECCNo
Controllers1
Channels4
Width32 bit
Max Bandwidth47.68 GiB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s
Quad 47.68 GiB/s

Expansions[edit]

  • PCI Express2.0 (1 lane) x 2 ch
  • USB 3.0 Host interface (DRD) × 1 ports (wPHY)
  • USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
  • SD Host interface × 4 ch (SDR104)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 1 ch
  • Media local bus (MLB) Interface × 1 ch (3 pin interface)
  • Controller Area Network (CAN-FD support) Interface × 2ch
  • Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
  • SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
  • Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
  • 32bit timer x 26 ch
  • PWM timer × 7 ch
  • I2C bus interface × 7 ch
  • Serial communication interface (SCIF) × 11 ch
  • Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)
  • Digital radio interface (DRIF) × 4 ch

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GX6650
DesignerImagination Technologies
Output

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions

Block Diagram[edit]

r-car h3 block.png

Die Shot[edit]

  • 16 nm process, CMOS FinFET
  • 12.94 mm × 8.61 mm
  • 111.36 mm² die size


r-car h3 die shot.png

References[edit]

  • Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H3 (SiP) - Renesas#package +
core count9 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.8 V (8 dV, 80 cV, 800 mV) +
designerRenesas + and ARM Holdings +
die area111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
familyR-Car +
first announcedDecember 2, 2015 +
first launchedMarch 2018 +
full page namerenesas/r-car/h3 (sip) +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size0.625 MiB (640 KiB, 655,360 B, 6.103516e-4 GiB) +
l1d$ size0.281 MiB (288 KiB, 294,912 B, 2.746582e-4 GiB) +
l1i$ size0.344 MiB (352 KiB, 360,448 B, 3.356934e-4 GiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateMarch 2018 +
main imageFile:r-car h3 (sip).png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberH3 (SiP) +
nameR-Car H3 (SiP) +
packageFCBGA-1255 +
part numberR8J77950 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count9 +
word size64 bit (8 octets, 16 nibbles) +