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R-Car H2 - Renesas
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R-Car H2
r-car h2.jpg
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberH2
Part NumberR8A7790
MarketEmbedded
IntroductionMarch 25, 2013 (announced)
June, 2014 (launched)
General Specs
FamilyR-Car
Series2nd Gen
Frequency1,500 MHz, 1,000 MHz, 780 MHz
Microarchitecture
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex A15, Cortex A7, SH-4A
Core NameCortex A15, Cortex A7, SH-4A
Process28 nm
TechnologyCMOS
Word Size32 bit
Cores9
Threads9
Max CPUs1 (Uniprocessor)
Electrical
Vcore1.0 V
VI/O3.3, 1.8
Packaging
PackageFCBGA-831 (BGA)
Dimension27 mm x 27 mm
Pitch0.80 mm
Ball Count831
InterconnectBGA-831

R-Car H2 is a high-end embedded nona-core SoC for the automotive industry introduced by Renesas in early 2013. The H2 incorporates four Cortex-A15 cores operating at 1.5 GHz, four Cortex-A7 cores operating at 1 GHz, and one SH-4A core operating at 780 MHz for real-time processing. This SoC incorporates Imagination's PowerVR G6400 GPU operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.

Cache[edit]

Main articles: Cortex-A15 § Cache and Cortex-A7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
0.563 MiB
589,824 B
5.493164e-4 GiB
L1I$288 KiB
0.281 MiB
294,912 B
2.746582e-4 GiB
9x32 KiB  
L1D$288 KiB
0.281 MiB
294,912 B
2.746582e-4 GiB
9x32 KiB  

L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 Host interface × 1 port (wPHY)
  • USB 2.0 Host interface × 3 port (wPHY)
  • SD Host interface × 4 ch (SDXC, UHS-I)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 8 ch
  • Serial communication interface (SCIF) × 10 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6400
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency550 MHz
0.55 GHz
550,000 KHz
Output

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram[edit]

r-car h2 block.png

Dev Board ("LAGER")[edit]

R-Car H2 dev board.png
  • 210 mm x 180 mm
  • R-Car H2
  • 68 MiB serial flash memory
  • 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
  • RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
  • HDMI and LVDS display-out
  • switches, LEDs, I/O expansion header
Facts about "R-Car H2 - Renesas"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H2 - Renesas#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) +
core count9 +
core nameCortex A15 +, Cortex A7 + and SH-4A +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedMarch 25, 2013 +
first launchedJune 2014 +
full page namerenesas/r-car/h2 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR G6400 +
integrated gpu base frequency550 MHz (0.55 GHz, 550,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size0.563 MiB (576 KiB, 589,824 B, 5.493164e-4 GiB) +
l1d$ size0.281 MiB (288 KiB, 294,912 B, 2.746582e-4 GiB) +
l1i$ size0.281 MiB (288 KiB, 294,912 B, 2.746582e-4 GiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateJune 2014 +
main imageFile:r-car h2.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory channels2 +
microarchitectureCortex A15 +, Cortex A7 + and SH-4A +
model numberH2 +
nameR-Car H2 +
packageFCBGA-831 +
part numberR8A7790 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count9 +
word size32 bit (4 octets, 8 nibbles) +