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SC2A11 - Socionext
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Socionext SC2A11
SC2A11 IMG01.jpg
General Info
DesignerSocionext, ARM Holdings
Model NumberSC2A11
MarketServer, Networking, IoT
IntroductionNovember 14, 2016 (announced)
2017 (launched)
General Specs
Frequency
1 GHz
1,000,000 kHz
1,000 MHz
Bus typeAMBA
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53
Core NameCortex-A53
TechnologyCMOS
Word Size
8 octets
16 nibbles
64 bit
Cores24
Threads24

SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
L1I$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
24x32 KiB2-way set associative 
L1D$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
24x32 KiB4-way set associative 

L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  2x256 KiB16-way set associative 

L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Channels2
Max Bandwidth15.89 GiB/s
Bandwidth
Single 15.89 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
UART

GP I/OYes

Graphics[edit]

This SoC has no integrated graphics processing unit.

Networking[edit]

  • 2x Gigabit Ethernet Interfaces

Storage[edit]

  • SPI
  • eMMC
Facts about "SC2A11 - Socionext"
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus typeAMBA +
core count24 +
core nameCortex-A53 +
designerSocionext + and ARM Holdings +
first announcedNovember 14, 2016 +
first launched2017 +
full page namesocionext/sc2a11 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l1d$ description4-way set associative +
l1d$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l1i$ description2-way set associative +
l1i$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l2$ description16-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate3000 +
main imageFile:SC2A11 IMG01.jpg +
market segmentServer +, Networking + and IoT +
max pcie lanes4 +
microarchitectureCortex-A53 +
model numberSC2A11 +
nameSocionext SC2A11 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count24 +
word size64 bit (8 octets, 16 nibbles) +