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R-Car M2 - Renesas
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R-Car M2
r-car m2.jpg
General Info
ARM Holdings
Model NumberM2
Part NumberR8A7791
IntroductionSeptember 26, 2013 (announced)
June, 2015 (launched)
General Specs
Series2nd Gen
Frequency1,500 MHz
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex-A15, SH-4A
Core NameCortex-A15, SH-4A
Process28 nm
Word Size32 bit
Max CPUs1 (Uniprocessor)
Vcore1.03 V
VI/O1.8 V, 3.3 V
PackageFCBGA-831 (BGA)
Dimension27 mm x 27 mm
Pitch0.80 mm
Ball Count831

R-Car M2 is a mid-range performance embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2013. The M2 incorporates two Cortex-A15 cores operating at 1.5 GHz and a third SH-4A core for real-time processing. This chip incorporates Imagination's PowerVR SGX544 GPU operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.


Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
0.188 MiB
196,608 B
1.831055e-4 GiB
L1I$96 KiB
0.0938 MiB
98,304 B
9.155273e-5 GiB
3x32 KiB  
L1D$96 KiB
0.0938 MiB
98,304 B
9.155273e-5 GiB
3x32 KiB  

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Width32 bit
Max Bandwidth11.92 GiB/s
Single 5.96 GiB/s
Double 11.92 GiB/s


  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 host interface × 1 port (wPHY)
  • USB 2.0 host interface × 2 ports (wPHY)
  • SD host interface × 3 ch (SDXC, UHS-I)
  • Multimedia card interface × 1 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 9 ch
  • Serial communication interface (SCIF) × 18 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
  • Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)


[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency520 MHz
0.52 GHz
520,000 KHz


[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram[edit]

r-car m2 block.png

Dev Board ("KOELSCH")[edit]

R-Car M2 dev board.png
  • 210 mm x 180 mm
  • R-Car M2
  • 68 MiB serial flash memory
  • 2 GiB DDR3-DRAM-1600; 2x 32-bit configuration
  • RS-232C, UART, USB, SD, LAN, SATA, PCIe, CAN, MLB interfaces (partially via connector)
  • HDMI and LVDS display-out
  • switches, LEDs, I/O expansion headers
Facts about "R-Car M2 - Renesas"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M2 - Renesas#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count3 +
core nameCortex-A15 + and SH-4A +
core voltage1.03 V (10.3 dV, 103 cV, 1,030 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedSeptember 26, 2013 +
first launchedJune 2015 +
full page namerenesas/r-car/m2 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX544 +
integrated gpu base frequency520 MHz (0.52 GHz, 520,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1d$ size0.0938 MiB (96 KiB, 98,304 B, 9.155273e-5 GiB) +
l1i$ size0.0938 MiB (96 KiB, 98,304 B, 9.155273e-5 GiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateJune 2015 +
main imageFile:r-car m2.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory channels2 +
microarchitectureCortex-A15 + and SH-4A +
model numberM2 +
nameR-Car M2 +
packageFCBGA-831 +
part numberR8A7791 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count3 +
word size32 bit (4 octets, 8 nibbles) +