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Exynos 9610 - Samsung
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Exynos 9610
Exynos79610.png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9610
MarketMobile
IntroductionMarch 22, 2018 (announced)
October, 2018 (launched)
General Specs
FamilyExynos
SeriesExynos 7
Frequency2,300 MHz, 1,600 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A73, Cortex-A53
Core NameCortex-A73, Cortex-A53
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max CPUs1 (Uniprocessor)

Exynos 9610 is a 64-bit ARM mid-range microprocessor designed by Samsung set to launch in late 2018. Manufactured on Samsung's 10 nm process, the 9610 features eight cores consisting of four Cortex-A73 big cores operating at up to 2.3 GHz and four Cortex-A53 little cores operating at up to 1.6 GHz. This processor incorporates a Mali-G72 MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as 802.11ac, Bluetooth 5.0, and a 24 MP ISP.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main articles: Cortex-A73 § Cache and Cortex-A55 § Cache


For the Cortex-A73 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3200
Supports ECCNo
Max Mem6 GiB
Frequency1600 MHz
Controllers4
Channels4
Width16 bit
Bandwidth
Single 2.98 GiB/s
Double 5.96 GiB/s
Quad 11.92 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G72
DesignerARM Holdings
Execution Units3Max Displays2
Frequency? MHz
"? MHz" is not a number.
OutputDSI

Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL12 (600 Mbps)
UE Cat UL13 (150 Mbps)

ISP[edit]

  • 24MP Rear
  • 24MP Front
  • 16MP+16MP Dual

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices[edit]

This list is incomplete; you can help by expanding it.

Facts about "Exynos 9610 - Samsung"
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) + and 1,600 MHz (1.6 GHz, 1,600,000 kHz) +
core count8 +
core nameCortex-A73 + and Cortex-A53 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedMarch 22, 2018 +
first launchedOctober 2018 +
full page namesamsung/exynos/9610 +
has 4g supporttrue +
has ecc memory supportfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G72 +
integrated gpu designerARM Holdings +
isaARMv8 +
isa familyARM +
ldate3000 +
main imageFile:Exynos79610.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory channels4 +
microarchitectureCortex-A73 + and Cortex-A53 +
model number9610 +
nameExynos 9610 +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesExynos 7 +
supported memory typeLPDDR4X-3200 +
technologyCMOS +
thread count8 +
user equipment category downlink12 +
user equipment category uplink13 +
word size64 bit (8 octets, 16 nibbles) +