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Hi1612 - HiSilicon
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Hi1612
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1612
MarketServer
IntroductionJune 4, 2016 (announced)
June 4, 2016 (launched)
General Specs
FamilyHi16xx
Frequency2,100 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57
Core NameCortex-A57
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max CPUs2 (Multiprocessor)
Max Memory256 GiB

Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.

Cache[edit]

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
L1I$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
32x48 KiB8-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
32x32 KiB8-way set associative 

L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 

L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels4
Width64 bit
Max Bandwidth63.58 GiB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 2x8

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices[edit]

  • HiSilicon D03
  • Huawei Taishan 2180

This list is incomplete; you can help by expanding it.

Facts about "Hi1612 - HiSilicon"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Hi1612 - HiSilicon#pcie +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count32 +
core nameCortex-A57 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedJune 4, 2016 +
first launchedJune 4, 2016 +
full page namehisilicon/kunpeng/hi1612 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
l1d$ description8-way set associative +
l1d$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateJune 4, 2016 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory channels4 +
microarchitectureCortex-A57 +
model numberHi1612 +
nameHi1612 +
process16 nm (0.016 μm, 1.6e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count32 +
used byHiSilicon D03 + and Huawei Taishan 2180 +
word size64 bit (8 octets, 16 nibbles) +