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R-Car M1S - Renesas
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R-Car M1S
General Info
DesignerRenesas
ManufacturerTSMC
Model NumberM1S
Part NumberR8A77780
MarketEmbedded
IntroductionFebruary 16, 2011 (announced)
June, 2012 (launched)
Release Price$65
General Specs
FamilyR-Car
Series1st Gen
Frequency800 MHz
Microarchitecture
ISASuperH (SuperH)
MicroarchitectureSH-4A
Core NameSH-4A
Process40 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Vcore1.2 V
VI/O3.3 V
Packaging
PackageFCBGA-472 (BGA)
Dimension21 mm x 21 mm
Pitch0.80 mm
Ball Count472
InterconnectBGA-472

R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
L1I$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
2x32 KiB4-way set associative 
L1D$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
2x32 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth3.97 GiB/s
Bandwidth
Single 3.97 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4

GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics[edit]

  • 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency200 MHz
0.2 GHz
200,000 KHz
Output

Standards
OpenGL2.1
OpenGL ES2.0

Block Diagram[edit]

rcar m1s block.png
Facts about "R-Car M1S - Renesas"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M1S - Renesas#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count1 +
core nameSH-4A +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerRenesas +
familyR-Car +
first announcedFebruary 16, 2011 +
first launchedJune 2012 +
full page namerenesas/r-car/m1s +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaSuperH +
isa familySuperH +
l1$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateJune 2012 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory channels1 +
microarchitectureSH-4A +
model numberM1S +
nameR-Car M1S +
packageFCBGA-472 +
part numberR8A77780 +
process40 nm (0.04 μm, 4.0e-5 mm) +
release price$ 65.00 (€ 58.50, £ 52.65, ¥ 6,716.45) +
series1st Gen +
supported memory typeDDR3-1066 + and DDR2-800 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +