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R-Car E2 - Renesas
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R-Car E2
r-car e2.jpg
General Info
ARM Holdings
Model NumberE2
Part NumberR8A7794
IntroductionOctober 22, 2014 (announced)
June, 2016 (launched)
General Specs
Series2nd Gen
Frequency1,000 MHz, 780 MHz
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex-A7, SH-4A
Core NameCortex-A7, SH-4A
Process28 nm
Word Size32 bit
Max CPUs1 (Uniprocessor)
Max Memory2 GiB
Vcore1.0 V
VI/O3.3 V, 1.8 V
PackageFCBGA-501 (BGA)
Dimension21 mm x 21 mm
Pitch0.80 mm
Ball Count501

R-Car E2 is an entry-level embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2014. The E2 incorporates two Cortex-A7 cores operating at 1 GHz along with a SH-4A core operating at 780 MHz for real-time processing. This chip includes an Imagination PowerVR SGX540 GPU operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.


Main article: Cortex-A7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
0.188 MiB
196,608 B
1.831055e-4 GiB
L1I$96 KiB
0.0938 MiB
98,304 B
9.155273e-5 GiB
3x32 KiB  
L1D$96 KiB
0.0938 MiB
98,304 B
9.155273e-5 GiB
3x32 KiB  

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333
Supports ECCNo
Max Mem2 GiB
Width32 bit
Max Bandwidth9.93 GiB/s
Single 4.97 GiB/s
Double 9.93 GiB/s


  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • USB 2.0 host interface × 2 ports (wPHY)
  • SD host interface × 3 ch (SDXC, UHS-I)
  • Multimedia card interface × 1 ch
  • I²C bus interface × 8 ch
  • Serial communication interface (SCIF) × 18 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
  • Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)


[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency260 MHz
0.26 GHz
260,000 KHz


[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram[edit]

r-car e2 block.png

Dev Board ("ALT")[edit]

R-Car E2 dev board.png
  • 210 mm x 160 mm
  • 68 MB serial flash & 8 GByte eMMC memory
  • 1 GB DDR3-DRAM-1333; 2 x 16-bit configuration
  • RS-232C, UART, 2x USB, SD, LAN, CAN
  • EtherAVB PHY Connetor
  • Video in (2ch)
  • RGB and LVDS display-out
  • switches, LEDs, I/O expansion headers
Facts about "R-Car E2 - Renesas"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car E2 - Renesas#package +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) +
core count3 +
core nameCortex-A7 + and SH-4A +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedOctober 22, 2014 +
first launchedJune 2016 +
full page namerenesas/r-car/e2 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency260 MHz (0.26 GHz, 260,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1d$ size0.0938 MiB (96 KiB, 98,304 B, 9.155273e-5 GiB) +
l1i$ size0.0938 MiB (96 KiB, 98,304 B, 9.155273e-5 GiB) +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateJune 2016 +
main imageFile:r-car e2.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory channels2 +
microarchitectureCortex-A7 + and SH-4A +
model numberE2 +
nameR-Car E2 +
packageFCBGA-501 +
part numberR8A7794 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
supported memory typeDDR3-1333 +
technologyCMOS +
thread count3 +
word size32 bit (4 octets, 8 nibbles) +