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Exynos 9810 - Samsung
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Exynos 9810
exynos 9810.png
General Info
DesignerSamsung, ARM Holdings
ManufacturerSamsung
Model Number9810
MarketMobile
IntroductionJanuary 3, 2018 (announced)
February 25, 2018 (launched)
General Specs
FamilyExynos
SeriesExynos 9
Frequency2,900 MHz, 1,900 MHz
Microarchitecture
ISAARMv8.3 (ARM)
MicroarchitectureMongoose 3, Cortex-A55
Core NameMongoose 3, Cortex-A55
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max CPUs1 (Uniprocessor)

Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a DynamiQ configuration consisting of 4 Mongoose 3 big cores operating at 2.9 GHz and 4 Cortex-A55 little cores operating at 1.9 GHz. This chip supports up to 6 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G72 MP18 GPU operating at 600 MHz. The 9810 incorporates an LTE modem supporting cat 18 download and cat 13 upload.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache

For the Mongoose 3 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
0.375 MiB
393,216 B
3.662109e-4 GiB
L1I$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
4x64 KiB4-way set associative 
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB8-way set associative 

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 MiB16-way set associative 

L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB  

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB2-way set associative 
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB4-way set associative 

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3600
Supports ECCNo
Max Mem6 GiB
Frequency1800 MHz
Controllers4
Channels4
Width16 bit
Bandwidth
Single 13.41 GiB/s
Double 26.82 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G72
DesignerARM Holdings
Execution Units18Max Displays2
Frequency600 MHz
0.6 GHz
600,000 KHz
OutputDSI

Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Codec Encode Decode
HEVC (H.265)
MPEG-4 AVC (H.264)
VP9

All at 4K UHD 120fps.

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL18 (1200 Mbps)
UE Cat UL13 (200 Mbps)

ISP[edit]

  • 24MP Rear
  • 24MP Front
  • 16MP+16MP Dual

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices[edit]

  • Samsung Galaxy S9
  • Samsung Galaxy S9+

This list is incomplete; you can help by expanding it.

Facts about "Exynos 9810 - Samsung"
base frequency2,900 MHz (2.9 GHz, 2,900,000 kHz) + and 1,900 MHz (1.9 GHz, 1,900,000 kHz) +
core count8 +
core nameMongoose 3 + and Cortex-A55 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedJanuary 3, 2018 +
first launchedFebruary 25, 2018 +
full page namesamsung/exynos/9810 +
has 4g supporttrue +
has ecc memory supportfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G72 +
integrated gpu base frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu designerARM Holdings +
isaARMv8.3 +
isa familyARM +
l1$ size0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1d$ description8-way set associative + and 4-way set associative +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + and 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateFebruary 25, 2018 +
main imageFile:exynos 9810.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
microarchitectureMongoose 3 + and Cortex-A55 +
model number9810 +
nameExynos 9810 +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesExynos 9 +
supported memory typeLPDDR4X-3600 +
technologyCMOS +
thread count8 +
used bySamsung Galaxy S9 + and Samsung Galaxy S9+ +
user equipment category downlink18 +
user equipment category uplink13 +
word size64 bit (8 octets, 16 nibbles) +