From WikiChip
R-Car H1 - Renesas
< renesas‎ | r-car

Edit Values
R-Car H1
r-car h1.png
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberH1
Part NumberR8A77790
MarketEmbedded
IntroductionOctober 21, 2011 (announced)
November, 2011 (launched)
General Specs
FamilyR-Car
Series1st Gen
Frequency800 MHz, 1000 MHz
Microarchitecture
ISAARMv7 (ARM)
MicroarchitectureCortex-A9, SH-4A
Core NameCortex-A9, SH-4A
Process40 nm
TechnologyCMOS
Word Size32 bit
Cores5
Threads5
Max CPUs1 (Uniprocessor)
Max Memory2 GiB
Electrical
Vcore1.2 V
VI/O3.3 V
Packaging
PackageFCBGA-832 (BGA)
Dimension27 mm x 27 mm
Pitch0.80 mm
Ball Count832
InterconnectBGA-832

R-Car H1 is a high-end embedded penta-core SoC for the automotive industry designed by Renesas and introduced in 2011. The H1 features 5 cores, four Cortex-A9 cores operating at 1 GHz and an additional SH-4A core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates Imagination's PowerVR SGX543-MP2 GPU. The H1 supports up to 2 GiB of dual-channel DDR3-1066 memory.

Announced in late 2011, Renesas expected mass production begin in December 2012 with a peak rate of 100,000 units per month by December 2013.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB4-way set associative 
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB4-way set associative 

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth7.95 GiB/s
Bandwidth
Single 3.97 GiB/s
Double 7.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes1
Configs1x1
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4

GP I/OYes
JTAGYes
  • 3 x HSPI
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 4 x SD

Graphics[edit]

  • Display out × 2 ch (RGB888)
  • Video input x 2 ch
  • Video decode processor (H.264/AVC, MPEG-4, VC-1)

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX543
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency250 MHz
0.25 GHz
250,000 KHz
Output

Standards
OpenGL2.0
OpenCL1.1
OpenGL ES2.0

Audio[edit]

  • Sound processing unit × 2 ch
  • Sampling rate converter × 10 ch
  • Sound serial interface × 10 ch
  • MOST DTCP

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution

Block Diagram[edit]

rcar h1 block.png


r-car h1 block.png

Dev Board ("MARZEN")[edit]

  • 200 mmx 150 mm
  • R-CAR H1
  • 64 MiB flash memory
  • 1 MiB serial flash/E²PROM
  • 2 x512 MiB DDR3-DRAM
  • RS-232C, UART,USB, SD, LAN, SATA, PCI, CAN, and MLB interfaces
  • Analog RGB with DSUB 15-pin and/or LVDS flat cable connector
  • switches,LEDs, I/O expansion
renesas marzen h1 board.png
Facts about "R-Car H1 - Renesas"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H1 - Renesas#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) + and 1,000 MHz (1 GHz, 1,000,000 kHz) +
core count5 +
core nameCortex-A9 + and SH-4A +
core voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedOctober 21, 2011 +
first launchedNovember 2011 +
full page namerenesas/r-car/h1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX543 +
integrated gpu base frequency250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 +
isa familyARM +
l1$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1d$ description4-way set associative +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ description4-way set associative +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateNovember 2011 +
main imageFile:r-car h1.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory channels2 +
max pcie lanes1 +
microarchitectureCortex-A9 + and SH-4A +
model numberH1 +
nameR-Car H1 +
packageFCBGA-832 +
part numberR8A77790 +
process40 nm (0.04 μm, 4.0e-5 mm) +
series1st Gen +
supported memory typeDDR3-1066 +
technologyCMOS +
thread count5 +
word size32 bit (4 octets, 8 nibbles) +