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{{title|Technology Node}}{{lithography processes}} | {{title|Technology Node}}{{lithography processes}} | ||
− | The '''technology node''' (also '''process node''', '''process technology''' or simply '''node''') refers to a specific [[semiconductor manufacturing process]] and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held | + | The '''technology node''' (also '''process node''', '''process technology''' or simply '''node''') refers to a specific [[semiconductor manufacturing process]] and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. |
− | + | Recent technology nodes such as [[22 nm]], [[16 nm]], [[14 nm]], and [[10 nm]] refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes. | |
− | + | Since around [[2017]] node names have been entirely overtaken by marketing with some leading-edge foundries using node names ambiguously to represent slightly modified processes. Additionally, the size, density, and performance of the transistors among foundries no longer matches between foundries. For example, Intel's [[10 nm]] is comparable to foundries [[7 nm]] while Intel's [[7 nm]] is comparable to foundries [[5 nm]]. | |
− | |||
− | |||
== History== | == History== | ||
{{see also|intel/process|dec/process|l1=Intel's Semiconductor Process History||l2=DEC's Semiconductor Process History}} | {{see also|intel/process|dec/process|l1=Intel's Semiconductor Process History||l2=DEC's Semiconductor Process History}} | ||
Line 13: | Line 11: | ||
<div style="display:inline-block; float: left; padding: 10px;">[[File:tech node.svg|100px]]</div> | <div style="display:inline-block; float: left; padding: 10px;">[[File:tech node.svg|100px]]</div> | ||
+ | |||
The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while [[DRAM]] development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of [[technology scaling]]. This continued to be the case well into the 2000s. The [[International Technology Roadmap for Semiconductors]] (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for [[Flash]], [[DRAM]], and [[MPU]]/[[ASIC]]. | The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while [[DRAM]] development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of [[technology scaling]]. This continued to be the case well into the 2000s. The [[International Technology Roadmap for Semiconductors]] (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for [[Flash]], [[DRAM]], and [[MPU]]/[[ASIC]]. | ||
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== Half node == | == Half node == | ||
Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. [[130 nm lithography process|130 nm]] after a full shrink yields [[90 nm lithography process|90 nm]]). Similarly, the associated '''half node''' was then expected to have a 0.9x linear shrink. The premise of this idea is that when a new technology node was being considered for a new full node, foundries design rules (e.g. [[standard cell]]s) were carefully designed with the expectation that a half node shrink was to follow after 18 months. When a half shrink finally took place, it was just a matter of various readjustments. Proper planning and proactive considerations during circuit design stages could allow seamless transition to the new process without encountering design rule violations, timing, or otherwise any reliability issues. Note that some steps such as [[packaging]] do need to be redesigned. | Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. [[130 nm lithography process|130 nm]] after a full shrink yields [[90 nm lithography process|90 nm]]). Similarly, the associated '''half node''' was then expected to have a 0.9x linear shrink. The premise of this idea is that when a new technology node was being considered for a new full node, foundries design rules (e.g. [[standard cell]]s) were carefully designed with the expectation that a half node shrink was to follow after 18 months. When a half shrink finally took place, it was just a matter of various readjustments. Proper planning and proactive considerations during circuit design stages could allow seamless transition to the new process without encountering design rule violations, timing, or otherwise any reliability issues. Note that some steps such as [[packaging]] do need to be redesigned. | ||
+ | |||
+ | == Nomenclature == | ||
+ | * The driving force behind process node scaling is [[Moore's Law]]. | ||
+ | :To achieve density doubling, the [[contacted poly pitch]] ([[CPP]]) and the [[minimum metal pitch]] ([[MMP]]) need to scale by roughly 0.7x each node. | ||
+ | :In other words, a scaling of <code>0.7x CPP ⋅ 0.7x MMP ≈ ½ area</code>. The node names are effectively a self-fulfilling prophecy driven by [[Moore's Law]]. | ||
+ | |||
+ | [[File:tech node naming.svg]] | ||
== Leading edge trend == | == Leading edge trend == | ||
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− | {| class="wikitable" style="text-align: center;" | + | {| class="wikitable" style="text-align: center; width: 100%; font-size: 90%;" |
− | ! colspan=" | + | ! colspan="15" | Number of Semiconductor Manufacturers (with a Cutting Edge Logic Fab) |
− | |- style="vertical-align: bottom; font-size: | + | |- style="vertical-align: bottom; font-size: 1em;" |
− | | | + | | |
+ | <!-- [[Altis Semiconductor|Altis]]<br> | ||
+ | [[Dongbu HiTek]]<br> | ||
[[SilTerra]]<br> | [[SilTerra]]<br> | ||
− | [[X-FAB]]<br> | + | [[X-FAB]]<br> --> |
− | |||
[[ADI]]<br> | [[ADI]]<br> | ||
[[Atmel]]<br> | [[Atmel]]<br> | ||
Line 42: | Line 49: | ||
[[Sanyo]]<br> | [[Sanyo]]<br> | ||
[[Mitsubishi]]<br> | [[Mitsubishi]]<br> | ||
− | [[ON]]<br> | + | [[ON Semi]]<br> |
[[Hitachi]]<br> | [[Hitachi]]<br> | ||
[[Cypress]]<br> | [[Cypress]]<br> | ||
+ | [[SkyWater]]<br> | ||
[[Sony]]<br> | [[Sony]]<br> | ||
[[Infineon]]<br> | [[Infineon]]<br> | ||
[[Sharp]]<br> | [[Sharp]]<br> | ||
[[Freescale]]<br> | [[Freescale]]<br> | ||
− | [[Renesas]] (NEC)<br> | + | [[Fujitsu]]<br> |
+ | [[Renesas]] ([[NEC]])<br> | ||
+ | [[TI]] (Texas Inst.)<br> | ||
[[Toshiba]]<br> | [[Toshiba]]<br> | ||
− | |||
− | |||
[[Panasonic]]<br> | [[Panasonic]]<br> | ||
− | [[STMicroelectronics]]<br> | + | [[STMicroelectronics|STMicro]]<br> |
[[HLMC]]<br> | [[HLMC]]<br> | ||
[[IBM]]<br> | [[IBM]]<br> | ||
[[UMC]]<br> | [[UMC]]<br> | ||
[[SMIC]]<br> | [[SMIC]]<br> | ||
− | [[AMD]]<br> | + | [[AMD]] (GF)<br> |
[[Samsung]]<br> | [[Samsung]]<br> | ||
[[TSMC]]<br> | [[TSMC]]<br> | ||
[[Intel]] | [[Intel]] | ||
− | | | + | | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
Cypress<br> | Cypress<br> | ||
+ | SkyWater<br> | ||
Sony<br> | Sony<br> | ||
Infineon<br> | Infineon<br> | ||
Sharp<br> | Sharp<br> | ||
Freescale<br> | Freescale<br> | ||
+ | Fujitsu<br> | ||
Renesas<br> | Renesas<br> | ||
− | |||
− | |||
TI<br> | TI<br> | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
Toshiba<br> | Toshiba<br> | ||
− | |||
− | |||
Panasonic<br> | Panasonic<br> | ||
− | + | STMicro<br> | |
<br> | <br> | ||
IBM<br> | IBM<br> | ||
Line 110: | Line 92: | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
+ | Fujitsu<br> | ||
Renesas<br> | Renesas<br> | ||
+ | TI<br> | ||
Toshiba<br> | Toshiba<br> | ||
− | |||
− | |||
Panasonic<br> | Panasonic<br> | ||
− | + | STMicro<br> | |
HLMC<br> | HLMC<br> | ||
IBM<br> | IBM<br> | ||
UMC<br> | UMC<br> | ||
SMIC<br> | SMIC<br> | ||
− | [[GlobalFoundries]] | + | GF<br> <!--[[GlobalFoundries]]--> |
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
+ | Fujitsu<br> | ||
Renesas<br> | Renesas<br> | ||
+ | TI<br> | ||
Toshiba<br> | Toshiba<br> | ||
− | |||
− | |||
Panasonic<br> | Panasonic<br> | ||
− | + | STMicro<br> | |
HLMC<br> | HLMC<br> | ||
IBM<br> | IBM<br> | ||
Line 140: | Line 122: | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
Panasonic<br> | Panasonic<br> | ||
− | + | STMicro<br> | |
HLMC<br> | HLMC<br> | ||
IBM<br> | IBM<br> | ||
Line 151: | Line 133: | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
IBM<br> | IBM<br> | ||
− | <br> | + | .<br> |
− | <br> | + | .<br> |
GF<br> | GF<br> | ||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
− | |||
UMC<br> | UMC<br> | ||
SMIC<br> | SMIC<br> | ||
Line 167: | Line 148: | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
− | <br> | + | .<br> |
+ | .<br> | ||
+ | Samsung<br> | ||
+ | TSMC<br> | ||
+ | Intel | ||
+ | | | ||
+ | <s>SMIC</s><br> | ||
+ | <s>GF</s><br> | ||
+ | Samsung<br> | ||
+ | TSMC<br> | ||
+ | Intel | ||
+ | | | ||
+ | ''SMIC''<br> | ||
+ | .<br> | ||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
− | | | + | | |
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
+ | <s>Intel</s> | ||
+ | | | ||
+ | .<br> | ||
+ | .<br> | ||
Intel | Intel | ||
+ | | | ||
+ | <s>''Samsung''</s><br> | ||
+ | ''TSMC''<br> | ||
+ | ''Intel'' | ||
+ | | | ||
+ | ''TSMC''<br> | ||
+ | ''Intel'' | ||
|- | |- | ||
+ | | [[180 nm]]<hr>[[130 nm]] | ||
+ | | [[90 nm]] | ||
+ | | [[65 nm]] | ||
+ | | [[45 nm]]<hr>([[40 nm]]) | ||
+ | | [[32 nm]]<hr>([[28 nm]]) | ||
+ | | [[22 nm]]<hr>([[20 nm]]) | ||
+ | | [[14 nm]]<hr>([[12 nm]]) <!-- [[16 nm]] TSMC --> | ||
+ | | [[10 nm]]<hr>([[8 nm]]) | ||
+ | | [[7 nm]]<hr>([[6 nm]]) | ||
+ | | [[5 nm]]<hr>([[4 nm]]) | ||
+ | | [[3 nm]]<hr>(25A) | ||
+ | | [[2 nm]]<hr>(20A) <!-- (Intel 20A) --> | ||
+ | | [[1.8 nm]]<hr>(18A) <!-- (Intel 18A) --> | ||
+ | | [[1.4 nm]]<hr>(14A) <!-- (Intel 14A) --> | ||
+ | | [[1 nm]]<hr>(10A) <!-- (Intel 10A) --> | ||
+ | |- | ||
+ | |} | ||
+ | |||
+ | === Timeline === | ||
+ | |||
+ | {| class="wikitable" style="text-align: center; width: 100%; font-size: 95%;" | ||
+ | ! colspan="20" | Timeline of Lithography Process (Technology node Semiconductor Manufacturing) | ||
+ | |- style="vertical-align: bottom; font-size: 1em;" | ||
+ | | [[1984]] | ||
+ | | [[1987]] | ||
+ | | [[1990]] | ||
+ | | [[1993]] | ||
+ | | [[1996]] | ||
+ | | [[1999]] | ||
+ | | [[2001]] | ||
+ | | [[2003]] | ||
+ | | [[2005]] | ||
+ | | [[2007]] | ||
+ | | [[2009]] | ||
+ | | [[2010]] | ||
+ | | [[2012]] | ||
+ | | [[2014]] | ||
+ | | [[2016]] | ||
+ | | [[2018]] | ||
+ | | [[2020]] | ||
+ | | [[2022]] | ||
+ | | [[2025]] | ||
+ | | [[2027]] | ||
+ | |- | ||
+ | | [[1 μm]] | ||
+ | | [[800 nm]] | ||
+ | | [[600 nm]] | ||
+ | | [[350 nm]] | ||
+ | | [[250 nm]] | ||
| [[180 nm]] | | [[180 nm]] | ||
| [[130 nm]] | | [[130 nm]] | ||
| [[90 nm]] | | [[90 nm]] | ||
| [[65 nm]] | | [[65 nm]] | ||
− | | [[45 nm]] | + | | [[45 nm]] <!--[[40 nm]]--> |
− | | [[32 nm]] | + | | [[32 nm]] |
− | | [[22 nm]] | + | | [[28 nm]] |
− | | [[ | + | | [[22 nm]] <!--[[20 nm]]--> |
− | | [[10 nm]] | + | | [[14 nm]] <!--[[12 nm]] ([[16 nm]] TSMC) --> |
− | | [[7 nm]] | + | | [[10 nm]] <!--[[8 nm]]--> |
− | | [[5 nm]] | + | | [[7 nm]] <!--[[6 nm]]--> |
+ | | [[5 nm]] <!--[[4 nm]]--> | ||
+ | | [[3 nm]] <!--(25A)--> | ||
+ | | [[2 nm]] <!-- (Intel 20A) --> | ||
+ | | [[1 nm]] <!-- (Intel 18A/14A) --> | ||
+ | |- | ||
|} | |} | ||
+ | <!-- | ||
+ | <pre> | ||
+ | (process nodes) | ||
+ | 20 μm – 1968 | ||
+ | 10 μm – 1971 | ||
+ | 6 μm – 1974 | ||
+ | 3 μm – 1977 | ||
+ | 1.5 μm – 1981 | ||
+ | 1 μm – 1984 | ||
+ | 800 nm – 1987 | ||
+ | 600 nm – 1990 | ||
+ | 350 nm – 1993 | ||
+ | 250 nm – 1996 | ||
+ | 180 nm – 1999 | ||
+ | 130 nm – 2001 | ||
+ | 90 nm – 2003 | ||
+ | 65 nm – 2005 | ||
+ | 45 nm – 2007 | ||
+ | 32 nm – 2009 | ||
+ | 28 nm – 2010 | ||
+ | 22 nm – 2012 | ||
+ | 14 nm – 2014 | ||
+ | 10 nm – 2016 | ||
+ | 7 nm – 2018 | ||
+ | 5 nm – 2020 | ||
+ | 3 nm – 2022 | ||
+ | Future | ||
+ | 2 nm ~ 2025 | ||
+ | 1 nm ~ 2027 | ||
+ | |||
+ | == Silicon Fabrication Tech == | ||
+ | |||
+ | === TSMC === | ||
+ | * TSMC 2 nanometer [updated] | ||
+ | Release Date: Q4-2024 Risk Production # | ||
+ | Trial run in Q1 2025: very successful # | ||
+ | Mass Production in Q1-2026 # | ||
+ | June 2020: TSMC is accelerating R&D | ||
+ | Sep 2020: fab construction has begun | ||
+ | Capacity end of 2025: up to 80,000 wafers per month # | ||
+ | 2026: 125,000 wafers per month # | ||
+ | Will use Gate-All-Around (GAA) technology | ||
+ | Probable VVIP customer: Apple # | ||
+ | First batch fully reserved for Apple # | ||
+ | Other customers: NVIDIA, AMD and Broadcom # | ||
+ | Multi-bridge channel field effect transistor (MBCFET) architecture | ||
+ | 10-15% speed improvement over N3 at same power, or 25-30% power at same speed | ||
+ | Several process variants: N2, N2P and N2X | ||
+ | Not using High-NA EUV # Nanosheet transistors | ||
+ | |||
+ | * TSMC 1.4 nanometer [updated] | ||
+ | Risk Trial Production: 2027 # | ||
+ | Mass Production: 2028 # | ||
+ | Ahead of schedule as of Apr 2025 # | ||
+ | Codename "A14" # Not using High-NA EUV # | ||
+ | |||
+ | * TSMC 1 nanometer | ||
+ | Release Date: around 2030 # | ||
+ | Fab construction: 2026 # | ||
+ | Uses Semi-metal bismuth for contact electrodes # | ||
+ | Chip plan planning has started as of Nov 2022 # | ||
+ | Codename "A10" # Uses High-NA EUV # | ||
+ | |||
+ | === Samsung === | ||
+ | * Samsung 3 nanometer | ||
+ | Mass Production: H1 2022 | ||
+ | "Initial production" started as of Jun 30th 2022 | ||
+ | Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET) | ||
+ | 45% less power while delivering 23% more performance | ||
+ | 35% less silicon space taken per transistor (vs. 7 nm) | ||
+ | 16% less silicon space taken per transistor (vs. 5 nm) | ||
+ | 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35% | ||
+ | Samsung claims 60-70% yields as of May 2023 # | ||
+ | In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC # | ||
+ | According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node # | ||
+ | Trial run of second-generation 3 nm process starting in early 2024 # | ||
+ | |||
+ | * Samsung 2 nanometer [updated] | ||
+ | Mass production: Q4 2025 # | ||
+ | Uses Multi-Bridge-Channel FET (MBCFETTM) | ||
+ | Feb 2024: order received for AI chips # | ||
+ | Possibly using backside power delivery # | ||
+ | Efficiency improved by 25%, performance by 12%, area by 5% # | ||
+ | Samsung's new Texas fab might be 2 nm # | ||
+ | Capacity in S3 foundry: 7000 wafers per month # | ||
+ | |||
+ | * Samsung 1.4 nanometer [updated] | ||
+ | In planning as of Oct 2022 | ||
+ | Plant construction: Q2 2025 # | ||
+ | Mass Production: 2027 or 2028 # | ||
+ | Could be canceled as of Mar 2025 # | ||
+ | GAA (gate-all-around) | ||
+ | 2.5D/3D integration, Micro-bumps | ||
+ | |||
+ | === Intel === | ||
+ | * Intel 20A | ||
+ | 20 Angstrom = 2 nanometers | ||
+ | Release Date: H1 2024 # | ||
+ | Cancelled for Foundry Customers # | ||
+ | New transistors called RibbonFET | ||
+ | PowerVia to connect silicon dies | ||
+ | 15% perf/watt improvement over Intel 3 # | ||
+ | |||
+ | * Intel 18A [updated] | ||
+ | 18 Angstrom = 1.8 nanometer | ||
+ | Release Date: H2 2025 # | ||
+ | First wafers produced in Arizona as of March 2025 # | ||
+ | Risk production as of April 2025 # | ||
+ | Intel expects to beat TSMC to this milestone # | ||
+ | Improvements to RibbonFET for higher transistor density # | ||
+ | 10% perf/watt improvement over Intel 20A # | ||
+ | Feb 2024: an order for Intel 18A has been placed by Faraday Technology Corp. for an Arm-based SOC # | ||
+ | NVIDIA and Broadcom testing 18 A # | ||
+ | Broadcom not happy with test results # | ||
+ | Density similar to TSMC # | ||
+ | Backside power delivery # | ||
+ | |||
+ | * Intel 14A | ||
+ | 14 Angstrom = 1.4 nanometer # | ||
+ | Release Date: Unknown # | ||
+ | 15% performance per watt over Intel 18A # | ||
+ | 20% increase in transistor density # | ||
+ | High-NA extreme ultraviolet (EUV) # | ||
+ | Also 14A-E process with additional 5% performance boost # | ||
+ | |||
+ | * Intel 10A | ||
+ | 10 Angstrom = 1 nanometer # | ||
+ | Release Date: end of 2027 # | ||
+ | |||
+ | === SMIC === | ||
+ | * SMIC 5 nanometer [added] | ||
+ | Release Date: 2025 # | ||
+ | Difficult due to readily available EUV equipment in China # | ||
+ | 40-50% more expensive than TSMC # | ||
+ | </pre> | ||
+ | --> | ||
+ | |||
+ | == See also == | ||
+ | :;[[intel/process|Intel Process]] | ||
+ | * [[Intel 10 nm|Intel 10]] • [[10 nm]] | ||
+ | * [[Intel 7]] • [[7 nm]] | ||
+ | * [[Intel 4]] • [[5 nm]] | ||
+ | * [[Intel 3]] • [[3 nm]] | ||
+ | * <s>[[Intel 20A]]</s> • [[2 nm]] | ||
+ | * [[Intel 18A]] • [[2 nm]] | ||
+ | * [[Intel 14A]] • [[TSMC A14]] | ||
+ | * [[Intel 10A]] • [[TSMC A10]] | ||
+ | [[Category:lithography]] | ||
[[Category:device fabrication]] | [[Category:device fabrication]] |
Latest revision as of 09:30, 20 April 2025
The technology node (also process node, process technology or simply node) refers to a specific semiconductor manufacturing process and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor including the gate length as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held.
Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes.
Since around 2017 node names have been entirely overtaken by marketing with some leading-edge foundries using node names ambiguously to represent slightly modified processes. Additionally, the size, density, and performance of the transistors among foundries no longer matches between foundries. For example, Intel's 10 nm is comparable to foundries 7 nm while Intel's 7 nm is comparable to foundries 5 nm.
Contents
[hide]History[edit]
Roughly for the first 35 years of the semiconductor history, since the first mass production of MOSFET in the 1960s to the late 1990s, the process node more or less referred to the transistor's gate length (Lg) which was also considered the "minimum feature size". For example, Intel's 0.5 µm process had Lg = 0.5 µm
. This lasted until the 0.25 µm process in 1997 at which point Intel started introducing more aggressive gate length scaling. For example, their 0.25 µm process had Lg = 0.20 µm
and likewise, their 0.18 µm process had Lg = 0.13 µm
(a node ahead). At those nodes the "process node" was effectively larger than the gate length.
The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while DRAM development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of technology scaling. This continued to be the case well into the 2000s. The International Technology Roadmap for Semiconductors (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for Flash, DRAM, and MPU/ASIC.
The ITRS traditionally defined the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process. It is a common metric used to describe and differentiate the technologies used in fabricating integrated circuits.
Meaning lost[edit]
At the 45 nm process, Intel reached a gate length of 25 nm on a traditional planar transistor. At that node the gate length scaling effectively stalled; any further scaling to the gate length would produce less desirable results. Following the 32 nm process node, while other aspects of the transistor shrunk, the gate length was actually increased.
With the introduction of FinFET by Intel in their 22 nm process, the transistor density continued to increase all while the gate length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (Weff = 2 * Hfin + Wfin
). Due to how the transistor changed dramatically from how it used to be, the current naming scheme lost any meaning.
Half node[edit]
Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. 130 nm after a full shrink yields 90 nm). Similarly, the associated half node was then expected to have a 0.9x linear shrink. The premise of this idea is that when a new technology node was being considered for a new full node, foundries design rules (e.g. standard cells) were carefully designed with the expectation that a half node shrink was to follow after 18 months. When a half shrink finally took place, it was just a matter of various readjustments. Proper planning and proactive considerations during circuit design stages could allow seamless transition to the new process without encountering design rule violations, timing, or otherwise any reliability issues. Note that some steps such as packaging do need to be redesigned.
Nomenclature[edit]
- The driving force behind process node scaling is Moore's Law.
- To achieve density doubling, the contacted poly pitch (CPP) and the minimum metal pitch (MMP) need to scale by roughly 0.7x each node.
- In other words, a scaling of
0.7x CPP ⋅ 0.7x MMP ≈ ½ area
. The node names are effectively a self-fulfilling prophecy driven by Moore's Law.
Leading edge trend[edit]
As shrinking becomes more complex, requiring more capital, expertise, and resources, the number of companies capable of providing leading edge fabrication has been steadily dropping. As of 2020, only three companies are now capable of fabricating integrated circuits on the most cutting edge process: Intel, Samsung, and TSMC.
Number of Semiconductor Manufacturers (with a Cutting Edge Logic Fab) | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADI |
Cypress |
Fujitsu |
Fujitsu |
Panasonic |
IBM |
UMC |
. |
|
SMIC |
Samsung |
Samsung |
. |
|
TSMC |
180 nm 130 nm |
90 nm | 65 nm | 45 nm (40 nm) |
32 nm (28 nm) |
22 nm (20 nm) |
14 nm (12 nm) |
10 nm (8 nm) |
7 nm (6 nm) |
5 nm (4 nm) |
3 nm (25A) |
2 nm (20A) |
1.8 nm (18A) |
1.4 nm (14A) |
1 nm (10A) |
Timeline[edit]
Timeline of Lithography Process (Technology node Semiconductor Manufacturing) | |||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1984 | 1987 | 1990 | 1993 | 1996 | 1999 | 2001 | 2003 | 2005 | 2007 | 2009 | 2010 | 2012 | 2014 | 2016 | 2018 | 2020 | 2022 | 2025 | 2027 |
1 μm | 800 nm | 600 nm | 350 nm | 250 nm | 180 nm | 130 nm | 90 nm | 65 nm | 45 nm | 32 nm | 28 nm | 22 nm | 14 nm | 10 nm | 7 nm | 5 nm | 3 nm | 2 nm | 1 nm |