Revision as of 03:24, 5 April 2017

Semiconductor lithography processes technology

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The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun with risk production in late 2016 and ramped up in mid-to-late 2017. This technology is set to be replaced by 7 nm process 2019.

Industry

Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) with production starting in the second half of 2017. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), plans ramp up mass production in May of 2017.

Due to marketing names the transistor sizes vary considerably between leading manufactures. For example, Intel's 10nm process is denser and smaller than TSMC's 7 nm process while Samsung's 10 nm process is more similar to Intel's 14 nm process.

Samsung

Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process.

Samsung 128 Mib SRAM demo 10 nm wafer
Technology 10nm FinFET Supply voltage 1.8 V (i/o) Bit cell size 0.040 µm² macro configs 256x512 Kib Capacity 256 Mib Test Features Programmable E-fuse Die Size 75.6mm2²

10 nm Microprocessors

• MediaTek
  • Helio
• Qualcomm
  • Snapdragon 800
  • Centriq
• Xiaomi
  • Surge

This list is incomplete; you can help by expanding it.

10 nm Microarchitectures

• Intel
  • Cannonlake
  • Icelake
  • Tigerlake
• Qualcomm
  • Falkor

This list is incomplete; you can help by expanding it.

Documents

• Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling

References

• Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
• Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
• Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
• Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
• Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.