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Tigerlake - Microarchitectures - Intel
| Tigerlake µarch | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 0.01 μm 10 nm
1.0e-5 mm |
| Succession | |
| ← | |
| Icelake | |
Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 10 nm process. Tigerlake is the "Optimization" microarchitecture as part of Intel's PAO model.
Process Technology[edit]
- Main article: Cannonlake § Process Technology
Tigerlake is set to use the same 10 nm process that was designed for Cannonlake.
See also[edit]
- AMD Zen 2
Facts about "Tigerlake - Microarchitectures - Intel"
| codename | Tigerlake + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tigerlake + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tigerlake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
