Difference between revisions of "32 nm lithography process"

Revision as of 18:19, 28 March 2017

Semiconductor lithography processes technology

The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

TSMC cancelled its planned 32nm node process.

Fab
Process Name
1st Production
Type
Wafer

Contacted Gate Pitch
Interconnect Pitch (M1P)
SRAM bit cell (HD)
SRAM bit cell (HS)
SRAM bit cell (LP)
DRAM bit cell

Common Platform IBM, Freescale, AMD		Intel		TSMC		Samsung		Toshiba / NEC		Common Platform 2 IBM, STMicroelectronics, Frescale, Chartered, Infineon
		P1268 (CPU) / P1269 (SoC)				32LP
2009		2009		2009		2009		2009		2010
PDSOI		Bulk
300mm
Value	45 nm Δ	Value	45 nm Δ	Value	40 nm Δ	Value	40 nm Δ	Value	40 nm Δ	Value	45 nm Δ
130 nm	0.68x	112.5 nm	0.63x	130 nm	0.80x	126 nm	0.98x	120 nm	0.71x	126 nm	0.66x
? nm	?x	112.5 nm	0.70x	? nm	?x	100 nm	0.85x	? nm	?x	100 nm	?x
0.15 µm²	0.41x	0.148 µm²	0.43x	0.15 µm²	0.62x	0.149 µm²	?x	0.124 µm²	0.64x	0.157 µm²	0.42x
		0.199 µm²
		0.171 µm²	0.45x
0.039 µm²	0.58x

Design Rules

Intel 32nm Design Rules
Layer	Pitch	Thick	Aspect Ratio	Image
Isolation	140 nm	200	-
Contacted Gate	112.5 nm	35 nm	--
Metal 1	112.5 nm	95 nm	1.7
Metal 2	112.5 nm	95 nm	1.7
Metal 3	112.5 nm	95 nm	1.7
Metal 4	168.8 nm	151 nm	1.8
Metal 5	225.0 nm	204 nm	1.8
Metal 6	337.6 nm	303 nm	1.8
Metal 7	450.1 nm	388 nm	1.7
Metal 8	566.5 nm	504 nm	1.8
Metal 9	19.4 µm	8 µm	1.5

Find models

Click to browse all 32 nm MPU models

32 nm Microprocessors

AMD
- A8
- A10
Intel
- Celeron
- Core i3
- Core i5
- Core i7
- Core i7EE
- Xeon
- Xeon E3
- Xeon E5
- Xeon E7
UC Davis
- KiloCore
Princeton
- Piton

This list is incomplete; you can help by expanding it.

32 nm Microarchitectures

Intel
AMD
- Bulldozer
- Piledriver

This list is incomplete; you can help by expanding it.

@@ Line 21: / Line 21: @@
 ! colspan="2" | Common Platform <info>[[IBM]], [[Freescale]], [[AMD]]</info> !! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / NEC !! colspan="2" | Common Platform 2<info>[[IBM]], [[STMicroelectronics]], [[Frescale]], [[Chartered]], [[Infineon]]</info>
 |- style="text-align: center;"
-| colspan="2" | || colspan="2" | P1268 (CPU) / P1269 (SoC) || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" |
+| colspan="2" | || colspan="2" | P1268 (CPU) / P1269 (SoC) || colspan="2" | || colspan="2" | 32LP || colspan="2" | || colspan="2" |
 |- style="text-align: center;"
 | colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2010
@@ Line 31: / Line 31: @@
 ! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ !! Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[45 nm]] Δ
 |-
-| 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 113.4 nm || 0.88x || 120 nm || 0.71x || 126 nm || 0.66x
+| 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 126 nm || 0.98x || 120 nm || 0.71x || 126 nm || 0.66x
 |-
-| ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 113.4 nm || 0.97x || ? nm || ?x || ?nm || ?x
+| ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 100 nm || 0.85x || ? nm || ?x || 100 nm || ?x
 |-
-| 0.15 µm<sup>2</sup> || 0.41x || 0.148 µm<sup>2</sup> || 0.43x || 0.15 µm<sup>2</sup> || 0.62x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || 0.64x || 0.157 µm<sup>2</sup> || 0.42x
+| 0.15 µm<sup>2</sup> || 0.41x || 0.148 µm<sup>2</sup> || 0.43x || 0.15 µm<sup>2</sup> || 0.62x || 0.149 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || 0.64x || 0.157 µm<sup>2</sup> || 0.42x
 |-
 | || || 0.199 µm<sup>2</sup> || || || || || || || || ||

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