(add A17 Pro) |
|||
(19 intermediate revisions by 15 users not shown) | |||
Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
− | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin | + | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023. |
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | ||
Line 11: | Line 11: | ||
<!-- Intel --> | <!-- Intel --> | ||
| process 1 fab = [[Intel]] | | process 1 fab = [[Intel]] | ||
− | | process 1 name = | + | | process 1 name = P1278 (CPU), P1279? (SoC) |
− | | process 1 date = | + | | process 1 date = 2H 2023 |
| process 1 lith = EUV | | process 1 lith = EUV | ||
| process 1 immersion = | | process 1 immersion = | ||
| process 1 exposure = SE | | process 1 exposure = SE | ||
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
− | | process 1 wafer size = 300 | + | | process 1 wafer size = 300 mm |
− | | process 1 transistor = | + | | process 1 transistor = FinFET |
| process 1 volt = | | process 1 volt = | ||
| process 1 delta from = [[5 nm]] Δ | | process 1 delta from = [[5 nm]] Δ | ||
Line 43: | Line 43: | ||
<!-- TSMC --> | <!-- TSMC --> | ||
| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = | + | | process 2 name = N3, N3E <info>N3 Enhanced</info> |
− | | process 2 date = | + | | process 2 date = 2H 2022 |
| process 2 lith = EUV | | process 2 lith = EUV | ||
| process 2 immersion = | | process 2 immersion = | ||
| process 2 exposure = SE | | process 2 exposure = SE | ||
| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
− | | process 2 wafer size = 300 | + | | process 2 wafer size = 300 mm |
− | | process 2 transistor = | + | | process 2 transistor = FinFET |
| process 2 volt = | | process 2 volt = | ||
| process 2 delta from = [[5 nm]] Δ | | process 2 delta from = [[5 nm]] Δ | ||
Line 75: | Line 75: | ||
<!-- Samsung --> | <!-- Samsung --> | ||
| process 4 fab = [[Samsung]] | | process 4 fab = [[Samsung]] | ||
− | | process 4 name = | + | | process 4 name = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around |
+ | | process 1 date = 1H 2022 | ||
+ | Plus</info> | ||
| process 4 date = | | process 4 date = | ||
| process 4 lith = EUV | | process 4 lith = EUV | ||
Line 81: | Line 83: | ||
| process 4 exposure = SE | | process 4 exposure = SE | ||
| process 4 wafer type = Bulk | | process 4 wafer type = Bulk | ||
− | | process 4 wafer size = 300 | + | | process 4 wafer size = 300 mm |
| process 4 transistor = GAA | | process 4 transistor = GAA | ||
| process 4 volt = | | process 4 volt = | ||
Line 106: | Line 108: | ||
| process 4 dram Δ = | | process 4 dram Δ = | ||
}} | }} | ||
− | + | ==== P1278 ==== | |
+ | Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe. | ||
=== Samsung === | === Samsung === | ||
On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown. | On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown. | ||
+ | |||
+ | === TSMC === | ||
+ | N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2. | ||
== 3 nm Microprocessors== | == 3 nm Microprocessors== | ||
+ | * Apple | ||
+ | ** {{apple|A17 Pro}} | ||
{{expand list}} | {{expand list}} | ||
Latest revision as of 15:58, 22 July 2024
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.
Contents
Industry[edit]
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | TSMC | Samsung | |||
---|---|---|---|---|---|
P1278 (CPU), P1279? (SoC) | N3, N3E N3 Enhanced |
3GAE 3nm Gate All Around Early , 3GAP3nm Gate All Around
| process 1 date = 1H 2022Plus | |||
2H 2023 | 2H 2022 | ||||
EUV | EUV | EUV | |||
SE | SE | SE | |||
Bulk | Bulk | Bulk | |||
300 mm | 300 mm | 300 mm | |||
FinFET | FinFET | GAA | |||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
N/A | |||||
P1278[edit]
Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe.
Samsung[edit]
On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
TSMC[edit]
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.
3 nm Microprocessors[edit]
- Apple
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
References[edit]
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017