From WikiChip
Difference between revisions of "3 nm lithography process"

m (David moved page 3.5 nm lithography process to 3 nm lithography process: Looks like Intel decided to call it "3")
(UPDATED)
 
(32 intermediate revisions by 21 users not shown)
Line 1: Line 1:
 
{{lithography processes}}
 
{{lithography processes}}
−
The '''3.5 nanometer (3.5 nm)''' or '''35 Å lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]].
+
The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023.
 +
 
 +
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
  
 
== Industry ==
 
== Industry ==
−
{{empty section}}
 
  
−
== 3.5 nm Microprocessors==
+
{{future information}}
 +
 
 +
{{finfet nodes comp
 +
<!-- Intel -->
 +
| process 1 fab          = [[Intel]]
 +
| process 1 name        = P1278 (CPU), P1279? (SoC)
 +
| process 1 date        = 2H 2023
 +
| process 1 lith        = EUV
 +
| process 1 immersion    = &nbsp;
 +
| process 1 exposure    = SE
 +
| process 1 wafer type  = Bulk
 +
| process 1 wafer size  = 300 mm
 +
| process 1 transistor  = FinFET
 +
| process 1 volt        = &nbsp;
 +
| process 1 delta from  = [[5 nm]] Δ
 +
| process 1 fin pitch    = &nbsp;
 +
| process 1 fin pitch Δ  = &nbsp;
 +
| process 1 fin width    = &nbsp;
 +
| process 1 fin width Δ  = &nbsp;
 +
| process 1 fin height  = &nbsp;
 +
| process 1 fin height Δ = &nbsp;
 +
| process 1 gate len    = &nbsp;
 +
| process 1 gate len Δ  = &nbsp;
 +
| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = &nbsp;
 +
| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = &nbsp;
 +
| process 1 sram hp      = &nbsp;
 +
| process 1 sram hp Δ    = &nbsp;
 +
| process 1 sram hd      = &nbsp;
 +
| process 1 sram hd Δ    = &nbsp;
 +
| process 1 sram lv      = &nbsp;
 +
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- TSMC -->
 +
| process 2 fab          = [[TSMC]]
 +
| process 2 name        = N3, N3E <info>N3 Enhanced</info>
 +
| process 2 date        = 2H 2022
 +
| process 2 lith        = EUV
 +
| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = SE
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 mm
 +
| process 2 transistor  = FinFET
 +
| process 2 volt        = &nbsp;
 +
| process 2 delta from  = [[5 nm]] Δ
 +
| process 2 fin pitch    = &nbsp;
 +
| process 2 fin pitch Δ  = &nbsp;
 +
| process 2 fin width    = &nbsp;
 +
| process 2 fin width Δ  = &nbsp;
 +
| process 2 fin height  = &nbsp;
 +
| process 2 fin height Δ = &nbsp;
 +
| process 2 gate len    = &nbsp;
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = &nbsp;
 +
| process 2 cpp Δ        = &nbsp;
 +
| process 2 mmp          = &nbsp;
 +
| process 2 mmp Δ        = &nbsp;
 +
| process 2 sram hp      = &nbsp;
 +
| process 2 sram hp Δ    = &nbsp;
 +
| process 2 sram hd      = &nbsp;
 +
| process 2 sram hd Δ    = &nbsp;
 +
| process 2 sram lv      = &nbsp;
 +
| process 2 sram lv Δ    = &nbsp;
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 +
<!-- Samsung -->
 +
| process 4 fab          = [[Samsung]]
 +
| process 4 name        = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around
 +
| process 1 date        = 1H 2022
 +
Plus</info>
 +
| process 4 date        = &nbsp;
 +
| process 4 lith        = EUV
 +
| process 4 immersion    = &nbsp;
 +
| process 4 exposure    = SE
 +
| process 4 wafer type  = Bulk
 +
| process 4 wafer size  = 300 mm
 +
| process 4 transistor  = GAA
 +
| process 4 volt        = &nbsp;
 +
| process 4 delta from  = [[5 nm]] Δ
 +
| process 4 fin pitch    = -
 +
| process 4 fin pitch Δ  =
 +
| process 4 fin width    =
 +
| process 4 fin width Δ  =
 +
| process 4 fin height  =
 +
| process 4 fin height Δ =
 +
| process 4 gate len    = &nbsp;
 +
| process 4 gate len Δ  = &nbsp;
 +
| process 4 cpp          = &nbsp;
 +
| process 4 cpp Δ        = &nbsp;
 +
| process 4 mmp          = &nbsp;
 +
| process 4 mmp Δ        = &nbsp;
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = &nbsp;
 +
| process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
 +
}}
 +
==== P1278 ====
 +
Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe.
 +
=== Samsung ===
 +
On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a  [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
 +
 
 +
=== TSMC ===
 +
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.
 +
 
 +
== 3 nm Microprocessors==
 +
* Apple
 +
** {{apple|A17 Pro}}
 +
* Apple
 +
** {{apple|M3}}
 +
* Apple
 +
** {{apple|M3 Pro}}
 +
* Apple
 +
** {{apple|M3 MAX}}
 
{{expand list}}
 
{{expand list}}
  
−
== 3.5 nm Microarchitectures==
+
== 3 nm Microarchitectures==
 
{{expand list}}
 
{{expand list}}
  
−
[[Category:Lithography]]
+
== References ==
 +
* Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after [[5 nm]], May 24, 2017
 +
 
 +
[[category:lithography]]

Latest revision as of 00:53, 18 September 2024

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC Samsung
P1278 (CPU), P1279? (SoC) N3, N3E
N3 Enhanced
 3GAE
3nm Gate All Around Early
, 3GAP
3nm Gate All Around 
| process 1 date         = 1H 2022
Plus
2H 2023 2H 2022  
EUV EUV EUV
     
SE SE SE
Bulk Bulk Bulk
300 mm 300 mm 300 mm
FinFET FinFET GAA
     
Value 5 nm Δ Value 5 nm Δ Value 5 nm Δ
        N/A
       
       
           
           
           
           
           
           
           

P1278[edit]

Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe.

Samsung[edit]

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

TSMC[edit]

N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.

3 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

3 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017
Retrieved from "https://en.wikichip.org/w/index.php?title=3_nm_lithography_process&oldid=102558"