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{{Lithography processes}}
 
{{Lithography processes}}
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The '''45 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[65 nm lithography process|65 nm process]]. Commercial [[integrated circuit]] manufacturing using 45 nm process began in 2007. This technology was superseded by the [[40 nm lithography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010.
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The '''45 nanometer (45 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[55 nm lithography process|55 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 45 nm process began in 2007. This technology was superseded by the [[40 nm lithography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010.
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== Industry ==
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In January of 2006 Intel announced that they've been able to fabricate the first fully functional [[SRAM]] chips on a 45 nm process. As a preview Intel showcased 45nm SRAM chip (shown below) packing more than 1 billion transistors. Intel opened 3 45 nm facilities, their initial {{intel|D1D}} facility in Oregon, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process.
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{{scrolling table/top|style=text-align: right; | first=Fab
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|Process Name
 +
|1st Production
 +
|Type
 +
|Wafer
 +
| 
 +
|Contacted Gate Pitch
 +
|Interconnect Pitch (M1P)
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|SRAM bit cell (HD)
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|SRAM bit cell (LP)
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|DRAM bit cell
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}}
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{{scrolling table/mid}}
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|-
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! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TI]] !! colspan="2" | [[Toshiba]] / [[Sony]] / [[NEC]]  !!  colspan="2" | [[Samsung]] !!  colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]]
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|- style="text-align: center;"
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| colspan="2" | P1266 (CPU) / P1266.8 (SoC) / P1269 (SoC) || colspan="2" | CS-300 || colspan="2" | || colspan="2" | || colspan="2" | 11LP || colspan="2" |
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|- style="text-align: center;"
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| colspan="2" | 2006 || colspan="2" | 2008 || colspan="2" | 2008 || colspan="2" | 2006 || colspan="2" | 2007 || colspan="2" | 2007
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|- style="text-align: center;"
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| colspan="10" | Bulk || colspan="2" | PDSOI
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|- style="text-align: center;"
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| colspan="12" | 300mm
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|-
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! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ
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|-
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| 180 nm || 0.82x || 190 nm || ?x || ? nm || ?x || 180 nm || ?x || ? nm || ?x || 190 nm || 0.76x
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|-
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| 160 nm || 0.76x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
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|-
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| 0.346 µm² || 0.61x || 0.225 µm² || ?x || 0.255 µm² || ?x || 0.248 µm² || ?x || 0.29 µm² || 0.54x || 0.370 µm² || 0.57x
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|-
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| 0.3816 µm² || 0.56x || || || || || || || 0.359 µm² || 0.53x || ||
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|-
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| || || || || || || || || 0.11 µm² || 0.58x || 0.067 µm² || 0.53x
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{{scrolling table/end}}
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=== Intel ===
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<gallery widths=200px heights=300px>
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File:45nm SRAM Cell.jpg|6T SRAM Bit-Cell
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File:45nm SRAM photo.JPG|Die photo of an [[Intel]] [[45 nm]] shuttle test chip including 153 MiB [[SRAM]] and logic test circuits
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File:45nm wafer photo 1.jpg|300 mm wafer with 45 nm shuttle test chips
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File:45nm wafer photo 2.JPG|Intel engineer holding 300 mm wafer with 45 nm shuttle test chips
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File:45nm-wafer-photo-3.jpg|Intel 300 mm wafer with 45 nm shuttle test chips
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</gallery>
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{| class="wikitable collapsible collapsed"
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|-
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! colspan="4" | Intel 45nm Design Rules
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|-
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! Layer !! Pitch !! Thick !! Aspect Ratio
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|-
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| Isolation || 200 nm || 200 nm || -
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|-
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| Contacted Gate || 180 nm || 60 nm || --
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|-
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| Metal 1 || 160 nm || 144 nm || 1.8
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|-
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| Metal 2 || 160 nm || 144 nm || 1.8
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|-
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| Metal 3 || 160 nm || 144 nm || 1.8
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|-
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| Metal 4 || 240 nm || 216 nm || 1.8
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|-
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| Metal 5 || 280 nm || 252 nm || 1.8
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|-
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| Metal 6 || 360 nm || 324 nm || 1.8
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|-
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| Metal 7 || 560 nm || 504 nm || 1.7
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|-
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| Metal 8 || 810 nm || 720 nm || 1.8
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|-
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| Metal 9 || 30.5 µm || 7 µm || 0.4
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|}
  
 
== 45 nm Microprocessors==
 
== 45 nm Microprocessors==
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{{expand list}}
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* AMD
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** {{amd|Athlon II}}
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** {{amd|Opteron}}
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** {{amd|Phenom II}}
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* Freescale
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** {{freescale|QorIQ}}
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* IBM
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** {{ibm|Power7}}
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* Intel
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** {{intel|Atom}}
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** {{intel|Celeron}}
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** {{intel|Core 2 Duo}}
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** {{intel|Core 2 Extreme}}
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** {{intel|Core 2 Quad}}
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** {{intel|Core 2 Quad Extreme}}
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** {{intel|Core 2 Solo}}
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** {{intel|Core i3}}
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** {{intel|Core i5}}
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** {{intel|Core i7}}
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** {{intel|Core i7EE}}
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** {{intel|Pentium Dual-Core}}
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** {{intel|Pentium (2009)|Pentium}}
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** {{intel|Xeon}}
  
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== 45 nm System on Chips==
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{{expand list}}n Chips==
 
{{expand list}}
 
{{expand list}}
  
 
== 45 nm Microarchitectures ==
 
== 45 nm Microarchitectures ==
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* Intel:
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* AMD
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** {{intel|Bonnell}}
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** {{amd|K10|l=arch}}
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* IBM
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** {{ibm|z196|l=arch}}
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* Intel
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** {{intel|Bonnell|l=arch}}
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** {{intel|Nehalem|l=arch}}
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** {{intel|Penryn|l=arch}}
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* VIA Technologies
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** {{via|Isaiah|l=arch}}
  
 
{{expand list}}
 
{{expand list}}
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 +
== Documents ==
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* [[:File:samsung foundry - 45, 65, 90 (August, 2007).pdf|Samsung foundry - 45 nm, 65 nm, 90 nm guide (August, 2007)]]
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* Intel
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** [[:File:45nmSummaryFoils.pdf|New Intel 45 nm Processors]]
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** [[:File:Press45nm107 FINAL.pdf|High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors]]
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** [[:File:SandToCircuit FINAL.pdf|From sand to circuits]]
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== References ==
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* Mistry, Kaizad, et al. "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
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[[category:lithography]]

Latest revision as of 04:51, 20 July 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 45 nanometer (45 nm) lithography process is a full node semiconductor manufacturing process following the 55 nm process stopgap. Commercial integrated circuit manufacturing using 45 nm process began in 2007. This technology was superseded by the 40 nm process (HN) / 32 nm process (FN) in 2010.

Industry[edit]

In January of 2006 Intel announced that they've been able to fabricate the first fully functional SRAM chips on a 45 nm process. As a preview Intel showcased 45nm SRAM chip (shown below) packing more than 1 billion transistors. Intel opened 3 45 nm facilities, their initial D1D facility in Oregon, Fab 32 in Arizona and Fab 28 in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process.

Fab
Process Name​
1st Production​
Type​
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (LP)​
DRAM bit cell
Intel Fujitsu TI Toshiba / Sony / NEC Samsung IBM / Toshiba / Sony / AMD
P1266 (CPU) / P1266.8 (SoC) / P1269 (SoC) CS-300 11LP
2006 2008 2008 2006 2007 2007
Bulk PDSOI
300mm
Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ
180 nm 0.82x 190 nm  ?x  ? nm  ?x 180 nm  ?x  ? nm  ?x 190 nm 0.76x
160 nm 0.76x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
0.346 µm² 0.61x 0.225 µm²  ?x 0.255 µm²  ?x 0.248 µm²  ?x 0.29 µm² 0.54x 0.370 µm² 0.57x
0.3816 µm² 0.56x 0.359 µm² 0.53x
0.11 µm² 0.58x 0.067 µm² 0.53x

Intel[edit]

  • 6T SRAM Bit-Cell

  • Die photo of an Intel 45 nm shuttle test chip including 153 MiB SRAM and logic test circuits

  • 300 mm wafer with 45 nm shuttle test chips

  • Intel engineer holding 300 mm wafer with 45 nm shuttle test chips

  • Intel 300 mm wafer with 45 nm shuttle test chips

45 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.n Chips== This list is incomplete; you can help by expanding it.

45 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

Documents[edit]

References[edit]

  • Mistry, Kaizad, et al. "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
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