Revision as of 01:00, 6 November 2017

Semiconductor lithography processes technology

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The 45 nanometer (45 nm) lithography process is a full node semiconductor manufacturing process following the 55 nm process stopgap. Commercial integrated circuit manufacturing using 45 nm process began in 2007. This technology was superseded by the 40 nm process (HN) / 32 nm process (FN) in 2010.

Industry

In January of 2006 Intel announced that they've been able to fabricate the first fully functional SRAM chips on a 45 nm process. As a preview Intel showcased 45nm SRAM chip (shown below) packing more than 1 billion transistors. Intel opened 3 45 nm facilities, their initial D1D facility in Oregon, Fab 32 in Arizona and Fab 28 in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process.

Intel

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  6T SRAM Bit-Cell

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  Die photo of an Intel 45 nm shuttle test chip including 153 MiB SRAM and logic test circuits

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  300 mm wafer with 45 nm shuttle test chips

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  Intel engineer holding 300 mm wafer with 45 nm shuttle test chips

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  Intel 300 mm wafer with 45 nm shuttle test chips

45 nm Microprocessors

• AMD
  • Athlon II
  • Opteron
  • Phenom II
• Freescale
  • QorIQ
• IBM
  • Power7
• Intel
  • Atom
  • Celeron
  • Core 2 Duo
  • Core 2 Extreme
  • Core 2 Quad
  • Core 2 Quad Extreme
  • Core 2 Solo
  • Core i3
  • Core i5
  • Core i7
  • Core i7EE
  • Pentium Dual-Core
  • Pentium
  • Xeon

This list is incomplete; you can help by expanding it.n Chips== This list is incomplete; you can help by expanding it.

45 nm Microarchitectures

• AMD
  • K10
• IBM
  • z196
• Intel
  • Bonnell
  • Nehalem
  • Penryn

This list is incomplete; you can help by expanding it.

Documents

• Samsung foundry - 45 nm, 65 nm, 90 nm guide (August, 2007)
• Intel
  • New Intel 45 nm Processors
  • High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors
  • From sand to circuits

References

• Mistry, Kaizad, et al. "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.