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<!-- TSMC --> | <!-- TSMC --> | ||
| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = N3, N3E<info>N3 Enhanced</info> | + | | process 2 name = N3(B), N3E <info>N3 Enhanced</info>, N3P, N3X |
| process 2 date = Q4 2022 | | process 2 date = Q4 2022 | ||
| process 2 lith = EUV | | process 2 lith = EUV | ||
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| process 2 gate len = | | process 2 gate len = | ||
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
− | | process 2 cpp = 45 nm (48) | + | | process 2 cpp = 45 nm (48 nm) |
| process 2 cpp Δ = | | process 2 cpp Δ = | ||
| process 2 mmp = 23 nm | | process 2 mmp = 23 nm | ||
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<!-- Samsung --> | <!-- Samsung --> | ||
| process 3 fab = [[Samsung]] | | process 3 fab = [[Samsung]] | ||
− | | process 3 name = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around Plus</info> | + | | process 3 name = 3GAE <info>3nm Gate All Around Early</info>, 3GAP <info>3nm Gate All Around Plus</info> |
| process 3 date = 2H 2022 | | process 3 date = 2H 2022 | ||
| process 3 lith = EUV | | process 3 lith = EUV | ||
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| process 3 sram lv Δ = | | process 3 sram lv Δ = | ||
| process 3 dram = | | process 3 dram = | ||
− | | process 3 dram Δ = | + | | process 3 dram Δ = <br>. |
}} | }} | ||
Latest revision as of 18:56, 19 March 2025
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing
- process following the 5 nm process node.
Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and
- does not represent any geometry of the transistor.
Contents
Industry[edit]
Intel[edit]
P1278 Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H 2024/2025 timeframe.
TSMC[edit]
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to
- 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website).
If this holds true we could see 300+ MT/mm2.
Samsung[edit]
On May 24, 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET
- (MBCFET), an extension of a Gate-all-around (GAA) FET.
This is planned for somewhere after the 5 nm node but the exact timeline or specification is currently unknown.
Specifications[edit]
Process Name | |
---|---|
1st Production | |
Litho- graphy |
Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Tran- sistor |
Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell |
High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell |
eDRAM |
Intel | TSMC | Samsung | |||
---|---|---|---|---|---|
P1278 (CPU), P1279 (SoC) | N3(B), N3E N3 Enhanced , N3P, N3X |
3GAE 3nm Gate All Around Early , 3GAP 3nm Gate All Around Plus
| |||
2H 2023 | Q4 2022 | 2H 2022 | |||
EUV | EUV | EUV | |||
SE | SE | SE | |||
Bulk | Bulk | Bulk | |||
300 mm | 300 mm | 300 mm | |||
FinFET | FinFET | GAAFET (MBCFET) | |||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
50 nm | 45 nm (48 nm) | 40 nm | |||
30 nm | 23 nm | 32 nm | |||
0.0199 μm2 | |||||
0.0210 μm2 | |||||
. |
3 nm process nodes[edit]
Samsung [1] | TSMC [2] | Intel [3] | |||||
---|---|---|---|---|---|---|---|
Process name | 3GAE (SF3E) | 3GAP (SF3) | N3 (N3B) | N3E | N3P | N3X | Intel 3 |
Transistor type | GAAFET (MBCFET) | FinFET | |||||
Transistor density (MTr/mm2) |
150 | 190 | 197 | 216 | 224 | - | |
Transistor gate pitch (nm) |
40 | - | 45 | 48 | - | - | 50 |
Interconnect pitch (nm) |
32 | - | - | 23 | - | - | 30 |
SRAM bit-cell size (μm2) |
- | - | 0.0199 | 0.021 | - | - | - |
Release status | 2022 H1 risk production 2022 H2 production 2022 shipping |
2024 Q1 risk production 2024 H2 production |
2022 H1 risk production 2022 H2 volume production 2023 H1 shipping |
2023 H2 production |
2024 H2 production |
2025 H2 production |
2024 H1 product manufacturing 2024 H2 shipping |
3 nm Microprocessors[edit]
- Qualcomm
- Snapdragon 8 Elite
- MediaTek
- Dimensity 9400
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures[edit]
4 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
References[edit]
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017