Revision as of 13:13, 1 June 2017

Semiconductor lithography processes technology

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The 10 nanometer (10 nm) lithography process is a semiconductor manufacturing process node serving as shrink from the 14 nm process. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 10 nm node is currently being introduced and is set to get replaced by the 7 nm process in 2019.

Industry

At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: Intel, Samsung, and TSMC.

Due to marketing names the transistor sizes vary considerably between leading manufactures. For example, Intel's 10nm process is denser and smaller than TSMC's 7 nm process while Samsung's 10 nm process is more similar to Intel's 14 nm process (e.g., a metal pitch just 1 nanometer shorter).

Intel

See also: Intel's Process Technology History

Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) with production starting in the second half of 2017. Intel detailed Hyper-Scaling, a marketing term for a suite of techniques used to scale a transistor, SAQP, a single dummy gate and contact over active gate (COAG).

Samsung

Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 mm contacted gate pitch, 51 nm metal pitch, dual-depth shallow trench isolation (STI), and had single dummy gate.

Samsung 128 Mib SRAM demo 10 nm wafer
Technology 10nm FinFET Supply voltage 1.8 V (i/o) Bit cell size 0.040 µm² macro configs 256x512 Kib Capacity 128 Mib Test Features Programmable E-fuse Die Size 75.6mm²

10 nm Microprocessors

• MediaTek
  • Helio
• Qualcomm
  • Snapdragon 800
  • Centriq
• Xiaomi
  • Surge

This list is incomplete; you can help by expanding it.

10 nm Microarchitectures

• Intel
  • Cannonlake
  • Icelake
  • Tigerlake
• Qualcomm
  • Falkor

This list is incomplete; you can help by expanding it.

Documents

• Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling
• Intel Technoogy & Manufacturing Day presentation, 10 nm
• Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law

References

• Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
• Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
• Seo, K-I., et al. "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
• Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
• Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
• Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.