Revision as of 19:13, 6 April 2017

Semiconductor lithography processes technology

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The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the self-aligned via patterning.

Design Rules

Intel 32nm Design Rules
Layer	Pitch	Thick	Aspect Ratio	Image
Isolation	140 nm	200	-
Contacted Gate	112.5 nm	35 nm	--
Metal 1	112.5 nm	95 nm	1.7
Metal 2	112.5 nm	95 nm	1.7
Metal 3	112.5 nm	95 nm	1.7
Metal 4	168.8 nm	151 nm	1.8
Metal 5	225.0 nm	204 nm	1.8
Metal 6	337.6 nm	303 nm	1.8
Metal 7	450.1 nm	388 nm	1.7
Metal 8	566.5 nm	504 nm	1.8
Metal 9	19.4 µm	8 µm	1.5
Bump	145.9 µm	25.5 µm	-

Find models

Click to browse all 32 nm MPU models

32 nm Microprocessors

• AMD
  • A8
  • A10
• Intel
  • Celeron
  • Core i3
  • Core i5
  • Core i7
  • Core i7EE
  • Xeon
  • Xeon E3
  • Xeon E5
  • Xeon E7
• UC Davis
  • KiloCore
• Princeton
  • Piton

This list is incomplete; you can help by expanding it.

32 nm Microarchitectures

• Intel
  • Saltwell
  • Sandy Bridge
  • Westmere
• AMD
  • Bulldozer
  • Piledriver

This list is incomplete; you can help by expanding it.

Documents

• Samsung foundry solution for 32 & 28 nm

References

• Greene, B., et al. "High performance 32nm SOI CMOS with high-k/metal gate and 0.149 µm 2 SRAM and ultra low-k back end with eleven levels of copper." VLSI Technology, 2009 Symposium on. IEEE, 2009.
• Jan, C-H., et al. "A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
• Wu, Shien-Yang, et al. "A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
• Chen, X., et al. "A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process." VLSI Technology, 2008 Symposium on. IEEE, 2008.
• Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
• Natarajan, S., et al. "A 32nm logic technology featuring 2 nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 μm 2 SRAM cell size in a 291Mb array." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
• Hasegawa, S., et al. "A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
• Arnaud, F., et al. "32nm general purpose bulk CMOS technology for high performance applications at low voltage." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
• Pilo, Harold, et al. "A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements." IEEE Journal of Solid-State Circuits 47.1 (2012): 97-106.