Difference between revisions of "amd/List of AMD CPU sockets"

Revision as of 18:32, 7 October 2025

Overview

Year	Desktop	Desktop APU	Server	Mobile	Tablet	Embedded
1998	Super 7 (321)			Super 7 (321)
1999	Slot A (242)
2000	Socket A (462)			Socket A (462)
2002				563
2003	754, 940		940	754
2004	939
2006	AM2, Fr3		F, L (1207FX)	S1g1
2007	AM2+		Fr2
2008			Fr5	S1g2
2009	AM3		Fr6	S1g3	ASB1
2010			C32, G34	S1g4	ASB2
2011		FM1		FS1	FT1	FT1
2012	AM3+	FM2		FS1r2, FP2		FP2
2013					FT3	FT3
2014		FM2+, AM1	SP1	FP3	FT3b	FP3, FT3b, SP1
2015				FP4		FP4
2016	AM4	AM4			FT4
2017	TR4		SP3 (Zen 2/3)
2018				FP5 (Zen/Zen+)		FP5, SP4, SP4r2
2019	sTRX4
2020	sWRX8			FP6 (Zen 2/3)	FT5 (Zen, Zen+)	FP6 (Zen 2/3)
2021		FF3 (Van Gogh)
2022	AM5	AM5	SP5 (Zen 4/5)	FP7	FT6 (Zen 2)	FP7
2023	sTR5	sTR5		FP7r2	FL1 (Zen 4/5)	FP7r2
2024			SP6 (Siena)	FP8, FP10		FP8, FP10
2025		FF5 (Sound Wave)	SP7 (Venice)	FP11, FP12		FP11, FP12
2026	AM6	AM6	SP8 (Venice)
2027

Desktop/HEDT/Workstation Sockets

Name (a.k.a.)	Year	Type^[1]	Contacts	AMD CPU ID	MC^[2]	I/O lanes^[3]	APU^[4]	FCH^[5]	Notes	Package^[6]
Super Socket 7	1998	PGA	321	5	-	FSB	✘	-
Slot A	1999	SEC	242	6	-	FSB	✘	-
Socket A	2000	PGA	462	6	-	FSB	✘	-		x50px
Socket 563	2003	PGA	563	6	-	FSB	✘	-
Socket 754	2003	PGA	754	0Fh	72 bit DDR	16 HT1	✘	-
Socket 940	2003	PGA	940	0Fh	144 bit DDR	3× 16 HT1	✘	-
Socket 939	2004	PGA	939	0Fh	144 bit DDR	16 HT1	✘	-
Socket AM2	2006	PGA	940	NPT 0Fh	144 bit DDR2	16 HT1	✘	-
Socket Fr3	2006	LGA	1207	NPT 0Fh	2× 72 bit DDR2	3 × 16 HT1	✘	-
Socket AM2+ (AM2r2)	2007	PGA	940	10h	2× 72 bit DDR2	16 HT3	✘	-
Socket AM3	2009	PGA	938	10h	2× 72 bit DDR2/3	16 HT3	✘	-
Socket FM1	2011	PGA	905	12h	2× 72 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe 2
Socket AM3+ (AM3b)	2012	PGA	941	15h	2× 72 bit DDR3	16 HT3	✘	-
Socket FM2	2012	PGA	904	15h	2× 64 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe 2
Socket AM1 (FS1b)	2014	PGA	721	16h	72 bit DDR3	4 + 4 PCIe 2	✔	integrated
Socket FM2+ (FM2b, FM2r2)	2014	PGA	906	15h	2× 64 bit DDR3	16 + 4 PCIe 2/3	✔	4 PCIe 2
Socket AM4	2016	PGA	1331	15h, 17h, 19h	2× 72 bit DDR3/4	16 + 4 PCIe 3/4	✔	4 PCIe 3/4
Socket TR4 (SP3r2)	2017	LGA	4094	17h	4× 72 bit DDR4	4× 16 PCIe 3	✘
Socket sTRX4 (SP3r3)	2019	LGA	4094	17h	4× 72 bit DDR4	4× 16 PCIe 4	✘
Socket sWRX8 (SP3r4)	2020	LGA	4094	17h, 19h	8× 72 bit DDR4	8× 16 PCIe 4	✘
Socket AM5	2022	LGA	1718	19h, 1Ah	2× 72 bit DDR5	16 + 4 + 4 PCIe 4/5	✔	4 PCIe 4/5	Zen 4/5
Socket sTR5	2023	LGA	4844	19h	8× 72 bit DDR5 (RDIMM w/ ECC)	8× 16 PCIe 5	✔	4 PCIe 4/5	TRX50, WRX90	x50px
Socket AM6	2026	LGA	2100	1Ah	2× 96 bit DDR6	8× 16 PCIe 6	✔	4 PCIe 6	Zen 7	x50px

↑ PGA = Pin Grid Array, BGA = Ball Grid Array (CPU package soldered directly to the motherboard), LGA = Land Grid Array, SEC = Single Edge Cartridge (printed circuit board with an edge connector similar to graphics cards).
↑ If processors for this socket integrate a Memory Controller, the number of independent channels times the maximum channel width in bits, including ECC lanes. Not all processors for this socket may support ECC.
↑ FSB = Front Side Bus (memory and I/O interfaces provided by the chipset), HTx = HyperTransport generation x link (I/O interfaces provided by the chipset), PCIex = Peripheral Component Interconnect Express generation x link. Note HT and PCIe links support bifurcation, e.g. 1x16 into 2x8 links. The table lists the maximum number of lanes and interfaces. Some processors may support fewer, and some motherboards may use alternative functions of these pins.
↑ This socket has graphics interfaces (DisplayPort, HDMI, VGA, etc.) to accommodate Accelerated Processing Units i.e. processors with integrated graphics. Not all processors for this socket may integrate a graphics processor.
↑ The number of dedicated I/O lanes to the Fusion Controller Hub a.k.a. chipset, equivalent to Intel's Platform Controller Hub. The FCH mainly serves as an I/O expander. A controller hub may be integrated on the processor, in this case the CPU package and socket has suitable I/O interfaces (USB, SATA, LPC, SMBus, etc.), sometimes in addition to the FCH interface.
↑ CPU package bottom view, not to scale.

Server Sockets

Name	Year	Type	Contacts	CPU Family	Memory Controller	I/O lanes	APU	SCH	Notes	Package
Socket 940	2003	PGA	940	0Fh	144 bit DDR	3× 16 HT1	✘	-	Athlon 64 FX, Opteron
Socket F	2006	LGA	1207	NPT 0Fh	2 × 72 bit DDR2	3× 16 HT1	✘	-	Athlon 64 FX, Opteron 2xxx/8xxx (multi)
Socket Fr2	2007	LGA	1207	NPT 0Fh, 10h	2× 72 bit DDR2	3× 16 HT1	✘	-
Socket Fr5	2008	LGA	1207	NPT 0Fh, 10h	2× 72 bit DDR2	3× 16 HT1/3	✘	-
Socket Fr6	2009	LGA	1207	10h	2× 72 bit DDR2	3× 16 HT3	✘	-
Socket C32	2010	LGA	1207	10h, 15h	2× 72 bit DDR3	3× 16 HT3	✘	-	Opteron 4xxx
Socket G34	2010	LGA	1944	10h, 15h	4× 72 bit DDR3	3× 16 + 2× 8 HT3	✘	-	Opteron 6xxx
Socket SP3	2017	LGA	4094	17h, 19h	8× 72 bit DDR4	8× 16 PCIe 3/4	✘	integrated	EPYC Naples Rome Milan
Socket SP5	2022	LGA	6096	19h, 1Ah	12× 80 bit DDR5	8× 16 PCIe 5	✘	integrated	EPYC 9004/9005 Genoa Turin
Socket SP6	2024	LGA	4844	19h	6× 80 bit DDR5	6× 16 PCIe 5	✘	integrated	EPYC 8004 Siena	x50px
Socket SP7	2025	LGA	7536	1Ah	16× 80 bit DDR5	128× PCIe Gen 6 + 16× PCIe Gen 4 (2P) 96× PCIe Gen 6 + 8× PCIe Gen 4 (1P)	✘	integrated	EPYC 9006/9007 Venice Verano	x50px
Socket SP8	2026	LGA	-	1Ah	8× 80 bit DDR5	192× PCIe Gen 6 + 16× PCIe Gen 4 (2P) 128× PCIe Gen 6 + 8× PCIe Gen 4 (1P)	✘	integrated	EPYC 9006 Venice	x50px

Mobile Sockets (mainstream)

Name	Year	Type	Pins	Fam.	MC	I/O lanes	APU	FCH	Notes	Package
Super Socket 7	1998	PGA	321	5	-	FSB	✘	-
Socket A	2000	PGA	462	6	-	FSB	✘	-
Socket 563	2003	PGA	563	6	-	FSB	✘	-
Socket 754	2003	PGA	754	0Fh	72 bit DDR	16 HT1	✘	-
Socket S1g1	2006	PGA	638	NPT 0Fh	144 bit DDR2	16 HT1	✘	-
Socket S1g2	2008	PGA	638	11h	2× 64 bit DDR2	16 HT3	✘	-
Socket S1g3	2009	PGA	638	10h	2× 64 bit DDR2	16 HT3	✘	-
Package ASB1	2009	BGA	812	NPT 0Fh	144 bit DDR2	16 HT1	✘	-
Socket S1g4	2010	PGA	638	10h	2× 64 bit DDR3	16 HT3	✘	-
Package ASB2	2010	BGA	812	10h	2× 72 bit DDR3	16 HT3	✘	-
Socket FS1	2011	PGA	722	12h	2× 64 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe 2
Socket FS1r2	2012	PGA	722	15h	2× 64 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe 2
Package FP2	2012	BGA	827	15h	2× 64 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe 2
Package FP3	2014	BGA	854	15h	2× 72 bit DDR3	16 + 8 PCIe 2/3	✔	4 PCIe 2
Package FP4	2015	BGA	968	15h, 16h	2× 72 bit DDR3/4	8 + 4 PCIe 3	✔	integrated
Package FP5	2018	BGA	1140	17h	2× 72 bit DDR4	8 + 8 PCIe 3	✔	integrated	Zen, Zen+
Package FP6	2020	BGA	1140	17h, 19h	2× 72 bit DDR4 4× 32 bit LPDDR4x	8 + 12 PCIe 3	✔	integrated	Zen 2, Zen 3
Package FP7 Package FP7r2	2022	BGA	1140	19h	4× DDR5-4800, 4× LPDDR5-6400	8 + 12 PCIe 4	✔	integrated	Zen 3+ Rembrandt
Package FP8	2024	BGA	1377	1Ah	4× DDR5-5600, 4× LPDDR5x-8000	16 PCIe 4	✔	integrated	Zen 5 Strix Point	x50px
Package FP10	2024	BGA	1384	1Ah	4× DDR5-5600, 4× LPDDR5x-8000	16 PCIe 4	✔	integrated	Zen 6 Medusa Point	x50px
Package FP11	2025	BGA	2077	1Ah	4× DDR5-5600, 4× LPDDR5x-8000	4 PCIe 5, 8 PCIe 4	✔	integrated	Zen 5 Strix Halo	x50px
Package FP12	2025	BGA	??	1Ah	4× 256-bit LPDDR5X, 4× 384-bit LPDDR6	4 PCIe 5, 8 PCIe 4	✔	integrated	Zen 6 Medusa Halo	x50px

Mobile Sockets (ultrathin, tablet)

Name	Year	Type	Pins	Famimy	MC	I/O lanes	APU	FCH	Notes
Package FT1	2011	BGA	413	14h	64 bit DDR3	4 PCIe 2	✔	4 PCIe 2
Package FT3	2013	BGA	769	16h	72 bit DDR3	4 PCIe 2	✔	4 PCIe 2
Package FT3b	2014	BGA	769	16h	72 bit DDR3	4 PCIe 2	✔	4 PCIe 2
Package FT4	2016	BGA	769	15h	64 bit DDR3/4	8 PCIe 3	✔	integrated
Package FT5	2020	BGA	-	17h	2× DDR4, LPDDR4	8 PCIe 3	✔	integrated	Zen
Package FT6	2022	BGA	-	17h	2× DDR5, LPDDR5	4 PCIe 3	✔	integrated	Zen 2
Package FL1	2023	BGA	1763	19h, 1Ah	2× DDR5, LPDDR5	4 PCIe 4	✔	integrated	Zen 4/5

Embedded Sockets

Name	Year	Type	Pins	Fam.	MC	I/O lanes	APU	FCH	Notes	Package
Package ASB1	2009	BGA	812	NPT 0Fh	144 bit DDR2	16 HT1	✘	-
Package ASB2	2010	BGA	812	10h	2× 72 bit DDR3	16 HT3	✘	-
Package FT1	2011	BGA	413	14h	64 bit DDR3	4 PCIe 2	✔	4 PCIe2
Package FP2	2012	BGA	827	15h	2× 64 bit DDR3	16 + 4 PCIe 2	✔	4 PCIe2
Package FT3	2013	BGA	769	16h	72 bit DDR3	4 PCIe 2	✔	4 PCIe2
Package FP3	2014	BGA	854	15h	2× 72 bit DDR3	16 + 8 PCIe 2/3	✔	4 PCIe2
Package SP1	2014	BGA	1021		2× 72 bit DDR3/4	8 PCIe 3	✘	integrated
Package FT3b	2014	BGA	769	16h	72 bit DDR3	4 PCIe 2	✔	4 PCIe2
Package FP4	2015	BGA	968	15h, 16h	2× 72 bit DDR3/4	8 + 4 PCIe 3	✔	integrated
Package FP5	2018	BGA	1140	17h	2× 72 bit DDR4	8 + 8 PCIe 3	✔	integrated
Socket SP3	2017	LGA	4094	17h	8× 72 bit DDR4	8× 16 PCIe 3	✘	integrated	^[1]
Package SP4	2018	BGA	2028	17h	4× 72 bit DDR4	4× 16 PCIe 3	✘	integrated		x50px
Package SP4r2	2018	BGA	2028	17h	2× 72 bit DDR4	2× 16 PCIe 3	✘	integrated		x50px
Package FP6	2020	BGA	1140	17h	2× 72 bit DDR4 4× 32 bit LPDDR4x	8 + 12 PCIe 3	✔	integrated

↑ Embedded versions of EPYC 7001 & 7002 processors, hence Family 17h only.

Game Consoles

Name	Year	Type	Pins	Family	MC	I/O	APU	FCH	Notes
Xbox One X BGA-2409	2017	BGA	2409	16h	12× 32 bit GDDR5	8 PCIe 3	✔
Xbox Series X/S BGA-2963	2020	BGA	2963	17h	20× 16 bit GDDR6	8 PCIe 4	✔	Arden ES	Lidless package with stiffener frame, 52.5 × 52.5 mm, 0.8+ mm multi-pitch^[1]^[2]

Microsoft XBOX Series X • ADN-A0 (Arden A0), XBX/BGA-2963, ADN-A0, Arden ES, 8C/16T, 8 MB, 3.60/3.80 GHz • MS XBOX
Microsoft XBOX Series S • ADN-A0 (Arden A0), XBS/BGA-2963, ADN-A0, Arden ES, 8C/16T, 8 MB, 3.40/3.60 GHz • MS XBOX
Sony Playstation 5 • ARL-A0 (Ariel A0), PS5/BGA ??, ARL-A0, Ariel ES/Oberon, 8C/16T, 32 MB, 1.60/3.20 GHz • Sony PS5

↑ Paternoster, Paul et al. XBOX SERIES X SoC – A Next Generation Gaming Console (Presentation, Slides). IEEE ISSCC 2021, 3.1. February 15, 2021
↑ Paternoster, Paul et al. (2021). XBOX Series X: A Next-Generation Gaming Console SoC. Proceedings of IEEE ISSCC 2021. pp. 46-48. doi:10.1109/ISSCC42613.2021.9366057

AMD CPU Packages

AMD CPU Packages
General				Details
Name	Package	Contacts	TDP	Socket	µarch	Market	Release
Package ASB1	ASB1, BGA-812	812	18 W 18,000 mW 0.0241 hp 0.018 kW		K8	Mobile	8 January 2009
Package ASB2	ASB2, BGA-812	812	15 W 15,000 mW 0.0201 hp 0.015 kW		K10	Mobile	12 May 2010
Package CBGA-360	CBGA-360	360	11 W 11,000 mW 0.0148 hp 0.011 kW		K6	Mobile	5 March 1998
Package FP2	BGA-827, FP2	827	25 W 25,000 mW 0.0335 hp 0.025 kW		Piledriver	Mobile, Embedded	15 May 2012
Package FP3	BGA-854, FP3	854	35 W 35,000 mW 0.0469 hp 0.035 kW		Steamroller	Mobile, Embedded	June 2014
Package FP4	BGA-968, FP4	968	45 W 45,000 mW 0.0603 hp 0.045 kW		Excavator	Mobile, Embedded	June 2015
Package FP5	BGA-1140	1,140	45 W 45,000 mW 0.0603 hp 0.045 kW		Zen, Zen+	Mobile, Embedded	8 January 2018
Package FP6	BGA-1140	1,140	55 W 55,000 mW 0.0738 hp 0.055 kW		Zen 2, Zen 3	Mobile, Embedded	16 March 2020
Package FT1	BGA-413, UOB-413	413	18 W 18,000 mW 0.0241 hp 0.018 kW		Bobcat	Mobile, Embedded	4 January 2011
Package FT3	BGA-769	769	25 W 25,000 mW 0.0335 hp 0.025 kW		Jaguar	Mobile, Embedded	May 2013
Package FT3b	BGA-769	769	25 W 25,000 mW 0.0335 hp 0.025 kW		Puma	Mobile, Embedded	4 June 2014
Package FT4	BGA-769	769	15 W 15,000 mW 0.0201 hp 0.015 kW		Excavator	Mobile	June 2016
Package OBGA-349	OBGA-349	349	18 W 18,000 mW 0.0241 hp 0.018 kW		K6	Embedded	25 September 2000
Package SP1	BGA-1021	1,021	32 W 32,000 mW 0.0429 hp 0.032 kW		Cortex-A57	Embedded, Server	January 2016
Package SP4	BGA-2028	2,028	100 W 100,000 mW 0.134 hp 0.1 kW		Zen	Embedded	21 February 2018
Package SP4r2	BGA-2028	2,028	55 W 55,000 mW 0.0738 hp 0.055 kW		Zen	Embedded	21 February 2018
Socket 563	OPGA-563, UOG 563	563	35 W 35,000 mW 0.0469 hp 0.035 kW	Socket 563	K7	Mobile	March 2003
Socket 754	OPGA-754	754	89 W 89,000 mW 0.119 hp 0.089 kW	Socket 754	K8	Desktop	23 September 2003
Socket 939	OPGA-939	939	110 W 110,000 mW 0.148 hp 0.11 kW	Socket 939	K8	Desktop	1 June 2004
Socket 940	CPGA-940	940	110 W 110,000 mW 0.148 hp 0.11 kW	Socket 940	K8	Server	22 April 2003
Socket AM1	OPGA-721	721	25 W 25,000 mW 0.0335 hp 0.025 kW	Socket AM1	Jaguar	Desktop	9 April 2014
Socket AM2	OPGA-940 AM2	940	125 W 125,000 mW 0.168 hp 0.125 kW	Socket AM2	K8	Desktop	23 May 2006
Socket AM2+	OPGA-940 (AM2)	940	140 W 140,000 mW 0.188 hp 0.14 kW	Socket AM2+	K10	Desktop	19 November 2007
Socket AM3	OPGA-938	938	125 W 125,000 mW 0.168 hp 0.125 kW	Socket AM3	K10	Desktop	9 February 2009
Socket AM3+	OPGA-940 (AM3)	940	220 W 220,000 mW 0.295 hp 0.22 kW	Socket AM3+	Bulldozer	Desktop	20 March 2012
Socket AM4	OPGA-1331	1,331	105 W 105,000 mW 0.141 hp 0.105 kW	Socket AM4	Zen	Desktop	September 2016
Socket AM5	LGA-1718	1,718	170 W 170,000 mW 0.228 hp 0.17 kW	Socket AM5	Zen 4	Desktop	18 April 2022
Socket C32	LGA-1207	1,207	95 W 95,000 mW 0.127 hp 0.095 kW	Socket C32	K10, Bulldozer, Piledriver	Server	23 June 2010
Socket F	LGA-1207	1,207	137 W 137,000 mW 0.184 hp 0.137 kW	Socket F	K8, K10	Server	15 August 2006
Socket FM1	OPGA-905	905	100 W 100,000 mW 0.134 hp 0.1 kW	Socket FM1	K10	Desktop	30 June 2011
Socket FM2	OPGA-904	904	100 W 100,000 mW 0.134 hp 0.1 kW	Socket FM2	Piledriver	Desktop	1 October 2012
Socket FM2+	OPGA-906	906	95 W 95,000 mW 0.127 hp 0.095 kW	Socket FM2+	Steamroller, Excavator	Desktop	31 July 2014
Socket FS1	OPGA-722	722	45 W 45,000 mW 0.0603 hp 0.045 kW	Socket FS1	K10	Mobile	14 June 2011
Socket FS1r2	OPGA-722	722	35 W 35,000 mW 0.0469 hp 0.035 kW	Socket FS1r2	Piledriver	Mobile	15 May 2012
Socket G34	LGA-1944	1,944	140 W 140,000 mW 0.188 hp 0.14 kW	Socket G34	K10, Bulldozer, Piledriver	Server	29 March 2010
Socket S1g1	OPGA-638	638	35 W 35,000 mW 0.0469 hp 0.035 kW	Socket S1g1	K8	Mobile	17 May 2006
Socket S1g2	OPGA-638	638	35 W 35,000 mW 0.0469 hp 0.035 kW	Socket S1g2		Mobile	4 June 2008
Socket S1g3	OPGA-638	638	35 W 35,000 mW 0.0469 hp 0.035 kW	Socket S1g3	K10	Mobile	10 September 2009
Socket S1g4	OPGA-638	638	45 W 45,000 mW 0.0603 hp 0.045 kW	Socket S1g4	K10	Mobile	12 May 2010
Socket SP3	SP3, FCLGA-4094	4,094	120 W 120,000 mW 0.161 hp 0.12 kW , 155 W 155,000 mW 0.208 hp 0.155 kW , 180 W 180,000 mW 0.241 hp 0.18 kW	SP3, LGA-4094	Zen, Zen 2, Zen 3	Server	20 June 2017
Socket SP5	SP5, FCLGA-6096	6,096	400 W 400,000 mW 0.536 hp 0.4 kW	Socket SP5	Zen 4	Server	10 November 2022
Socket TR4	TR4, FCLGA-4094	4,094	180 W 180,000 mW 0.241 hp 0.18 kW , 250 W 250,000 mW 0.335 hp 0.25 kW	TR4, SP3r2, sTR4	Zen, Zen+	Desktop, Workstation	10 August 2017
Socket sTRX4	sTRX4, FCLGA-4094	4,094	280 W 280,000 mW 0.375 hp 0.28 kW	sTRX4	Zen 2	HEDT	25 November 2019
Socket sWRX8	sWRX8, FCLGA-4094	4,094	280 W 280,000 mW 0.375 hp 0.28 kW	sWRX8	Zen 2, Zen 3	Workstation	14 July 2020
Super Socket 7	CPGA-321	321	30 W 30,000 mW 0.0402 hp 0.03 kW	Super Socket 7	K6	Desktop	May 1998

AMD CPU Sockets

Desktop sockets

Socket 940 (2003)
Socket 939 (2004)
Socket AM2 (2006)
Socket AM2+ (2007)
Socket AM3 (2009)
Socket AM3+ (2011)
Socket FM1 (2011)
Socket FM2 (2012)
Socket FM2+ (2014)
Socket AM1 (2014)
Socket AM4 (2016)
Socket TR4 (2017)
Socket sTRX4 (2019)
Socket sWRX8 (2020)
Socket AM5 (2022)
Socket sTR5 (2023)
Socket AM6 (2026)

Mobile sockets

Socket 563 (2002)
Socket S1 (2006)
Socket FS1 (2011)
Package FT1 (2011)
Package FP2 (2012)
Package FT3 (2013)
Package FP3 (2014)
Package FP4 (2015)
Package FT4 (2016)
Package FP5 (2019)
Package FP6 (2020)
Package FT5 (2020)
Package FT6 (2022)
Package FP7 (2022)
Package FL1 (2023)
Package FP8, FP10 (2024)
Package FP11, FP12 (2025)

Combined sockets

Super Socket 7 (1998) • [CPGA-321]
Slot A (Desktop) (1999)
Socket A (2000)
Socket 754 (2003)

Server sockets

Socket 940 (2003)
Socket F (2006)
Fr2, Fr3, Fr5, Fr6 (F+)
Socket C32 (2010)
Socket G34 (2010)
Package SP1 (2014)
Socket SP3 (2017)
Package SP4 (2018)
Socket SP5 (2022)
Socket SP6 (2023)
Socket SP7 (2025)
Socket SP8 (2026)

AMD APU

The following table shows features of AMD's processors with 3D graphics

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
	Server	Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne		Raphael
		Entry	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló	Rembrandt	Dragon Range	Phoenix
		Entry	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge												Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge	Dalí	Pollock		Mendocino
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"^[1]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+^[2]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	n/a												AM5	n/a	n/a
		Mainstream	n/a					AM4						n/a	AM5	n/a
		Entry	FM1	FM2		FM2+		FM2+, AM4	AM4					n/a
		Basic	n/a														n/a	AM1	n/a			FP5	n/a
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCIe version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			n/a														n/a
Fab (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC 4nm (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm²)			228	246		245		245	250	210 ^[3]		156	180	210	CCD: (2x) 70 cIOD: 122	178	75 (+ 28 FCH)	107		-	125	149			~100
Min TDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
Max CPU cores per APU			4									8			16	8	2	4			2			4
Max threads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR5-5600, LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2														1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen^[4]				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen^[4]	GCN 5th gen			RDNA 2

AMD Sockets (x86)

Table legend:

• Intel • AMD

Socket name	Year of introduction	CPU families	Computer type	Package	Pin count	Pin pitch (mm)	Bus clock & transfers	Notes
PGA168	?	AMD 486 Cyrix 486 Intel 80486		PGA	168	2.54	16–50 MHz	Sometimes referred to as Socket 0 or Socket 486
Socket 1	1989	AMD 486 AMD 5x86 Cyrix 486 Cyrix 5x86 Intel 80486		PGA	169	2.54	16–50 MHz
Socket 2	?	AMD 486 AMD 5x86 Cyrix 486 Cyrix 5x86 Intel 80486 Intel Pentium OverDrive (P24T) Intel DX4		PGA	238	2.54	16–50 MHz
Socket 3	1991	AMD 486 AMD 5x86 Cyrix 486 Cyrix 5x86 Intel 80486 Intel Pentium OverDrive (P24T) Intel DX4 IBM Blue Lightning		PGA	237	2.54	16–50 MHz
Socket 5	1994	AMD K5 Cyrix 6x86 IDT WinChip C6 IDT WinChip 2 Intel Pentium		PGA	320	?	50–100 MHz
Socket 7	1994	Intel Pentium Intel Pentium MMX AMD K6		PGA	321	?	50–66 MHz	It is possible to use Socket 7 processors in a Socket 5.
Super Socket 7	1998	AMD K6-2 AMD AMD K6-III Rise mP6 Cyrix 6x86 (MII)		PGA	321	?	66–100 MHz	Backward compatible with Socket 5 and Socket 7 processors.
Slot A	1999	AMD Athlon	Desktop	Slot	242	?	100 MHz
Socket A/ Socket 462 (OPGA-453)	2000	AMD Athlon AMD Duron AMD Athlon XP AMD Athlon XP-M AMD Athlon MP AMD Sempron	Desktop	PGA	462	?	100–200 MHz 400 MT/s
Socket 563	2002	AMD Athlon XP-M	Notebook	PGA	563	?	333 MHz
Socket 754	2003	AMD Athlon 64 AMD Sempron AMD Turion 64	Desktop	PGA	754	1.27	200–800 MHz
Socket 940	2003	AMD Opteron AMD Athlon 64 FX	Desktop Server	PGA	940	1.27	200–1000 MHz
Socket 939	2004	AMD Athlon 64 AMD Athlon 64 FX AMD Athlon 64 X2 AMD Opteron	Desktop	PGA	939	1.27	200–1000 MHz	Support of Athlon 64 FX to 1 GHz Support of Opteron limited to 100-series only
Socket S1	2006	AMD Turion 64 X2	Notebook	PGA	638	1.27	200–800 MHz
Socket AM2	2006	AMD Athlon 64 AMD Athlon 64 X2	Desktop	PGA	940	1.27	200–1000 MHz	Replaces Socket 754 and Socket 939
Socket F/ Socket L (Socket 1207FX)	2006	AMD Athlon 64 FX (Socket L) AMD Opteron	Desktop Server	LGA	1207	1.1	Socket L: 1000 MHz in Single CPU mode, 2000 MHz in Dual CPU mode	Replaces Socket 940
Socket AM2+	2007	AMD Athlon 64 AMD Athlon X2 AMD Phenom AMD Phenom II	Desktop	PGA	940	1.27	200–2600 MHz	Separated power planes Replaces Socket AM2
Socket AM3	2009	AMD Phenom II AMD Athlon II AMD Sempron AMD Opteron (1300 series)	Desktop	PGA	941^[5] or 940	1.27	200–3200 MHz	Separated power planes Replaces Socket AM2+
Socket G34	2010	AMD Opteron (6000 series)	Server	LGA	1974	?	200–3200 MHz	Replaces Socket F
Socket C32	2010	AMD Opteron (4000 series)	Server	LGA	1207	?	200–3200 MHz	Replaces Socket F, Socket AM3
Socket FM1	2011	AMD Llano	Desktop	PGA	905	1.27	5.2 GT/s	used for 1st generation APUs
Socket FS1	2011	AMD Llano	Notebook	PGA	722	1.27	3.2 GT/s	used for 1st generation Mobile APUs
Socket AM3+	2011	AMD (Bulldozer/Piledriver core/FX Vishera) AMD (Bulldozer/FX Zambezi) AMD Phenom II AMD Athlon II AMD Sempron	Desktop	PGA	942 (CPU 71pin)	1.27	3.2 GT/s
Socket FM2	2012	AMD Trinity	Desktop	PGA	904	1.27	?	used for 2nd generation APUs
Socket FM2+	2014	AMD Steamroller/Kaveri AMD Steamroller/Godavari	Desktop	PGA	906	1.27	?	Compatible with AMD APUs such as "Richland" and "Trinity"
Socket AM1	2014	AMD Athlon AMD Sempron	Desktop	PGA	721	1.27	?	Compatible with AMD APUs such as "Kabini"
Socket AM4	2016	AMD Athlon "Bristol Ridge" AMD Athlon "Raven Ridge" (14nm) AMD Athlon "Picasso" (12nm) AMD Ryzen (1000/2000/3000/4000/5000 series)	Desktop	PGA	1331	1	Depends on DDR4 speed	compatible with AMD Ryzen 9, Ryzen 7, Ryzen 5 & Ryzen 3 Zen based processors
Socket SP3	2017	AMD EPYC Naples AMD EPYC Rome AMD EPYC Milan	Server	LGA	4094	?	Depends on DDR4 speed	compatible with AMD EPYC processors
Socket TR4/ Socket SP3r2	2017	AMD Ryzen Threadripper (Whitehaven, Zen based), 1000 series) AMD Ryzen Threadripper (Colfax, Zen+ based), 2000 series)	Desktop	LGA	4094	?	Depends on DDR4 speed	compatible with AMD Ryzen Threadripper processors
Socket sTRX4/ Socket SP3r3	2019	AMD Ryzen Threadripper (Castle Peak, Zen 2 based, 3000 series)	Desktop	LGA	4094	?	Depends on DDR4 speed	compatible with 3rd generation AMD Ryzen Threadripper processors
Socket sWRX8	2022	AMD Ryzen Threadripper Pro (Chagall, Zen 3 based, 5000 series)	Desktop	LGA	4094
Socket AM5	2022	AMD Ryzen (7000 series) AMD Ryzen (8000 series) (APU) AMD Ryzen (9000 series)	Desktop	LGA	1718			Zen 4 Ryzen CPUs
Socket SP5	2022	AMD EPYC Genoa	Server	LGA	6096			Used for EPYC Genoa and Milan
Socket SP6	2023	AMD EPYC Siena	Server	LGA	4844
Socket sTR5	2023	AMD Ryzen Threadripper AMD Ryzen Threadripper Pro Storm Peak (7000 series, Zen 4)	Desktop	LGA	4844
Socket name	Year of introduction	CPU families	Computer type	Package	Pin count	Pin pitch (mm)	Bus clock & transfers	Notes

Packages to Scale

SP4/SP4r2

XBox Series X/S

↑ (31 May 2016) AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks.
↑ (20 November 2014) AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015.
↑ The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List. TechARP.com.
↑ ^4.0 ^4.1 AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver. VideoCardz.com.
↑ CPU only has 938 pins, but the socket has 941.

[1] PGA = Pin Grid Array, BGA = Ball Grid Array (CPU package soldered directly to the motherboard), LGA = Land Grid Array, SEC = Single Edge Cartridge (printed circuit board with an edge connector similar to graphics cards).

[2] If processors for this socket integrate a Memory Controller, the number of independent channels times the maximum channel width in bits, including ECC lanes. Not all processors for this socket may support ECC.

[3] FSB = Front Side Bus (memory and I/O interfaces provided by the chipset), HTx = HyperTransport generation x link (I/O interfaces provided by the chipset), PCIex = Peripheral Component Interconnect Express generation x link. Note HT and PCIe links support bifurcation, e.g. 1x16 into 2x8 links. The table lists the maximum number of lanes and interfaces. Some processors may support fewer, and some motherboards may use alternative functions of these pins.

[4] This socket has graphics interfaces (DisplayPort, HDMI, VGA, etc.) to accommodate Accelerated Processing Units i.e. processors with integrated graphics. Not all processors for this socket may integrate a graphics processor.

[5] The number of dedicated I/O lanes to the Fusion Controller Hub a.k.a. chipset, equivalent to Intel's Platform Controller Hub. The FCH mainly serves as an I/O expander. A controller hub may be integrated on the processor, in this case the CPU package and socket has suitable I/O interfaces (USB, SATA, LPC, SMBus, etc.), sometimes in addition to the FCH interface.

[6] CPU package bottom view, not to scale.

[7] Embedded versions of EPYC 7001 & 7002 processors, hence Family 17h only.

[ISSCC2021-XSX-8] Paternoster, Paul et al. XBOX SERIES X SoC – A Next Generation Gaming Console (Presentation, Slides). IEEE ISSCC 2021, 3.1. February 15, 2021

[Paternoster2021-9] Paternoster, Paul et al. (2021). XBOX Series X: A Next-Generation Gaming Console SoC. Proceedings of IEEE ISSCC 2021. pp. 46-48. doi:10.1109/ISSCC42613.2021.9366057

[10] (31 May 2016) AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks.

[11] (20 November 2014) AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015.

[12] The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List. TechARP.com.

[Vega_codenames-13] 4.0 ^4.1 AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver. VideoCardz.com.

[941note-14] CPU only has 938 pins, but the socket has 941.

[1

[2

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[4

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[6

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Revision as of 18:32, 7 October 2025

Contents

Overview

Desktop/HEDT/Workstation Sockets

Server Sockets

Mobile Sockets (mainstream)

Mobile Sockets (ultrathin, tablet)

Embedded Sockets

Game Consoles

AMD CPU Packages

AMD CPU Sockets

AMD APU

AMD Sockets (x86)

Packages to Scale

@@ Line 504: / Line 504: @@
 * {{amd|SP8|Socket SP8|l=package}} (2026)
 |}
+===AMD APU===
+The following table shows features of [[AMD]]'s processors with 3D graphics
+<!--, including {{When pagename is
+| List of AMD processors with 3D graphics = [[AMD APU|APU]]s.
+| AMD APU = APUs (see also: [[List of AMD processors with 3D graphics]]).
+| other = [[AMD APU|APU]]s (see also: [[List of AMD processors with 3D graphics]]).}}
+{{navbar-table|Features of AMD Processors with 3D Graphics}}
+-->
+{| class="wikitable" style="font-size: 85%; text-align: center"
+! colspan=3 | Platform
+! colspan=14 | High, standard and low power
+! colspan=9 | Low and ultra-low power
+|-
+! rowspan=11 | Codename || rowspan=2 | Server
+! | Basic
+! colspan=5 |
+! [[Toronto]]
+! colspan=8 |
+! colspan=9 |
+|-
+! | Micro
+! colspan=14 |
+!
+! [[Kyoto]]
+! colspan=7 |
+|-
+! rowspan=4 | Desktop
+! | Performance
+! colspan=12 |
+! rowspan=2 | [[Raphael]]
+! rowspan="3" | [[Phoenix]]
+! colspan=9 rowspan=3 |
+|-
+! | Mainstream
+! rowspan=2 | [[Llano]]
+! rowspan=2 | [[Trinity]]
+! rowspan=2 | [[Richland]]
+! rowspan=2 | [[Kaveri]]
+! rowspan=2 | [[Kaveri Refresh]] (Godavari)
+! rowspan=2 | [[Carrizo]]
+! rowspan=2 | [[Bristol Ridge]]
+! rowspan=2 | [[Raven Ridge]]
+! rowspan=2 | [[Picasso]]
+! rowspan=2 | [[Renoir]]
+! rowspan=2 | [[Cezanne]]
+!
+|-
+! | Entry
+! colspan="2" |
+|-
+! | Basic
+! colspan=14 |
+!
+! [[Kabini]]
+! colspan=3 |
+! [[Dalí]]
+! colspan=3 |
+|-
+! rowspan=4 | Mobile ||  | Performance
+! colspan=9 |
+! [[Renoir]]
+! [[Cezanne]]
+! rowspan=2 | [[Rembrandt]]
+! rowspan=2 | [[Dragon Range]]
+!
+! rowspan=2 colspan=9 |
+|-
+! | Mainstream
+! rowspan=2 | [[Llano]]
+! rowspan=2 | [[Trinity]]
+! rowspan=2 | [[Richland]]
+! rowspan=2 | [[Kaveri]]
+! rowspan=2 |
+! rowspan=2 | [[Carrizo]]
+! rowspan=2 | [[Bristol Ridge]]
+! rowspan=2 | [[Raven Ridge]]
+! [[Picasso]]
+! [[Renoir]]<br>[[Lucienne]]
+! [[Cezanne]]<br>[[Barceló]]
+! [[Phoenix]]
+|-
+! | Entry
+! colspan=6 |
+! colspan=5 |
+! rowspan=2 | [[Dalí]]
+! colspan=2 |
+! rowspan=2 | [[Mendocino]]
+|-
+! | Basic
+! colspan=14 |
+! Desna, Ontario, Zacate
+! Kabini, Temash
+! Beema, Mullins
+! Carrizo-L
+! [[Stoney Ridge]]
+! [[Pollock]]
+!
+|-
+! colspan=2 | Embedded
+!
+! Trinity
+!
+! Bald Eagle
+!
+! Merlin Falcon,<br>Brown Falcon
+!
+! [[List_of_AMD_processors_with_3D_graphics#V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)|Great Horned Owl]]
+!
+! [[Grey Hawk]]
+! colspan=4 |
+! Ontario, Zacate
+! Kabini
+! Steppe Eagle, Crowned Eagle,<br>LX-Family
+!
+! Prairie Falcon
+! [[Banded Kestrel]]
+!
+! [[River Hawk]]
+!
+|-
+| colspan=3 | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014
+| 2015 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2019 || Mar 2020
+| Jan 2021 || Jan 2022 || Sep 2022 || Jan 2023 || Jan 2011 || May 2013 || Apr 2014 || May 2015 || Feb 2016 || Apr 2019 || Jul 2020 || Jun 2022 || Nov 2022
+|-
+| colspan=3 | CPU [[microarchitecture]]
+| [[AMD 10h|K10]]
+| colspan=2 | [[Piledriver (microarchitecture)|Piledriver]]
+| colspan=2 | [[Steamroller (microarchitecture)|Steamroller]]
+| [[Excavator (microarchitecture)|Excavator]]
+| "[[Excavator (microarchitecture)|Excavator+]]"<ref>{{cite book |url=https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks |title=AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks |date=31 May 2016 |access-date=3 January 2020}}</ref>
+| [[Zen]]
+| [[Zen+]]
+| [[Zen 2]]
+| [[Zen 3]]
+| [[Zen 3+]]
+| colspan=2 | [[Zen 4]]
+| [[Bobcat (microarchitecture)|Bobcat]]
+| [[Jaguar (microarchitecture)|Jaguar]]
+| [[Puma (microarchitecture)|Puma]]
+| [[Puma (microarchitecture)|Puma+]]<ref>{{cite book |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=20 November 2014 |access-date=16 February 2015}}</ref>
+| "[[Excavator (microarchitecture)|Excavator+]]"
+| colspan=2 | [[Zen]]
+| [[Zen+]]
+| "[[Zen 2|Zen 2+]]"
+|-
+| colspan=3 | [[Instruction set architecture|ISA]] || [[x86-64]] v1 || colspan=4 | [[x86-64]] v2 || colspan=7 | [[x86-64]] v3 || colspan=2 | [[x86-64]] v4 || [[x86-64]] v1 || colspan=3 | [[x86-64]] v2 || colspan=5 | [[x86-64]] v3
+|-style="border-top:0.2em solid grey"
+| rowspan=5 | [[:Template:AMD CPU sockets|Socket]]
+| rowspan=4 | Desktop
+| | Performance
+| colspan=12 | n/a
+| rowspan=2 | [[Socket AM5|AM5]]
+| n/a
+| rowspan=3 colspan=9 | n/a
+|-
+| | Mainstream
+| colspan=5 | n/a
+| colspan=6 | [[Socket AM4|AM4]]
+| n/a
+| n/a
+|-
+| | Entry
+| [[Socket FM1|FM1]]
+| colspan=2 | [[Socket FM2|FM2]]
+| colspan=2 | [[Socket FM2+|FM2+]]
+| [[Socket FM2+|FM2+]],<!--{{efn|For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845|name=|group=}}--> [[Socket AM4|AM4]]
+| colspan=5 | [[Socket AM4|AM4]]
+| colspan=3 | n/a
+|-
+| | Basic
+| colspan=14 | n/a
+| n/a
+| [[Socket AM1|AM1]]
+| colspan=3 | n/a
+| [[Socket FP5|FP5]]
+| colspan=3 | n/a
+|-
+| colspan=2 | Other
+| [[Socket FS1|FS1]]
+| colspan=2 | [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]]
+| colspan=2 | [[Socket FP3|FP3]]
+| colspan=2 | [[Socket FP4|FP4]]
+| colspan=2 | [[Socket FP5|FP5]]
+| colspan=2 | [[Socket FP6|FP6]]
+| [[Socket FP7|FP7]]
+| FL1
+| FP7 <br> FP7r2 <br> FP8
+| [[Socket FT1|FT1]]
+| [[Socket FT3|FT3]]
+| colspan=2 | [[Socket FT3b|FT3b]]
+| [[Socket FP4|FP4]]
+| [[Socket FP5|FP5]]
+| [[Socket FT5|FT5]]
+| [[Socket FP5|FP5]]
+| [[Socket FT6|FT6]]
+|-
+| colspan=3 | [[PCI Express|PCIe]] version
+| colspan=3 | 2.0
+| colspan=8 | 3.0
+| 4.0
+| 5.0
+| 4.0
+| colspan=4 | 2.0
+| colspan=5 | 3.0
+|-
+| colspan=3 | [[Compute Express Link|CXL]] || colspan=14 | n/a
+| colspan=9 | n/a
+|-style="border-top:0.2em solid grey"
+| colspan=3 | [[Semiconductor device fabrication|Fab]] (nm)
+| colspan=3 | [[GlobalFoundries|GF]] [[32 nm process|32SHP]]<br>([[HKMG]] [[Silicon on insulator|SOI]])
+| colspan=4 | GF [[32 nm process|28SHP]]<br>(HKMG bulk)
+| GF [[14 nm process|14LPP]]<br>([[FinFET]] bulk)
+| GF [[14 nm process|12LP]]<br>(FinFET bulk)
+| colspan=2 | [[TSMC]] [[7 nm process|N7]]<br>(FinFET bulk)
+| TSMC [[7 nm process|N6]]<br> (FinFET bulk)
+| CCD: TSMC [[5 nm process|N5]]<br> (FinFET bulk) <br>cIOD: TSMC [[7 nm process|N6]]<br>(FinFET bulk)
+| TSMC [[5 nm process|4nm]]<br> (FinFET bulk)
+| TSMC [[45 nm process|N40]]<br>(bulk)
+| TSMC [[32 nm process|N28]]<br>(HKMG bulk)
+| colspan=3 | GF 28SHP<br>(HKMG bulk)
+| colspan=2 | GF [[14 nm process|14LPP]]<br>([[FinFET]] bulk)
+| GF [[14 nm process|12LP]]<br>(FinFET bulk)
+| TSMC [[7 nm process|N6]]<br> (FinFET bulk)
+|-
+| colspan=3 | [[Die (integrated circuit)|Die]] area (mm<sup>2</sup>) || 228 || colspan=2 | 246 || colspan=2 | 245 || 245 || 250 || colspan=2 | 210 <ref>{{cite book |title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List |url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |access-date=13 December 2017 |publisher=TechARP.com}}</ref> || 156
+| 180 || 210 || CCD: (2x) 70<br>cIOD: 122
+| 178|| 75 (+ 28 [[Fusion controller hubs|FCH]]) || colspan=2 | 107 || - || 125 || 149 || || || ~100
+|-
+| colspan=3 | Min [[Thermal Design Power|TDP]] (W) || 35 || colspan=4 | 17 || colspan=4 | 12 || colspan=2 | 10 || 15 || 65 || 35 || 4.5 || 4 || 3.95 || 10 || colspan=3 | 6 || 12 || 8
+|-
+| colspan=3 | Max APU [[Thermal Design Power|TDP]] (W) || colspan=3 | 100 || colspan=2 | 95 || colspan=6 | 65 || 45 || 170 || 54 || 18 || colspan=5 | 25 || 6 || 54 || 15
+|-
+| colspan=3 | Max stock APU base clock (GHz) || 3 || 3.8 || 4.1 || colspan=2 | 4.1 || 3.7 || 3.8 || 3.6 || 3.7 || 3.8 || 4.0 || 3.3 || 4.7 || 4.3 || 1.75 || 2.2 || 2 || 2.2 || 3.2 || 2.6 || 1.2 || 3.35 || 2.8
+|-
+| colspan=3 | Max APUs per node <!--{{efn|name=nodedef|A PC would be one node.}}--> || colspan=14 | 1 || colspan=9 | 1
+|-
+| colspan=3 | Max core dies per CPU || colspan=12 | 1 || 2 || 1 || colspan=9 | 1
+|-
+| colspan=3 | Max CCX per core die || colspan=9 | 1 || 2 || colspan=4 | 1 || colspan=9 | 1
+|-
+| colspan=3 | Max cores per CCX || colspan=10 | 4 || colspan=4 | 8 || 2 || colspan=3 | 4 || colspan=3 | 2 || colspan=2 | 4
+|-
+| colspan=3 | Max [[Central processing unit|CPU]] <!--{{efn|name=apudef|An APU combines a CPU and a GPU. Both have cores.}}--> [[Multi-core processor|cores]] per APU || colspan=9 | 4 || colspan=3 | 8 || 16 || 8 || 2 || colspan=3 | 4 || colspan=3 | 2 || colspan=2 | 4
+|-
+| colspan=3 | Max threads per CPU core || colspan=7 | 1 || colspan=7 | 2 || colspan=5 | 1 || colspan=4 | 2
+|-
+| colspan=3 | Integer pipeline structure || 3+3 || colspan=6 | 2+2 || colspan=2 | 4+2 || 4+2+1 || colspan=4 | 1+3+3+1+2 || colspan=4 | 1+1+1+1 || 2+2 || colspan=3 | 4+2 || 4+2+1
+|- <!--
+| colspan=3 | i386, i486, i586, CMOV, NOPL, i686, [[Physical_Address_Extension|PAE]], [[NX bit]], CMPXCHG16B, [[AMD-V]], [[Second_Level_Address_Translation#RVI|RVI]], [[Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)|ABM]], and 64-bit LAHF/SAHF || colspan=14 {{ya}}
+| colspan=9 {{ya}}
+|-
+| {{rh}} colspan=3 | [[IOMMU]]{{efn|name=iommubios|Requires firmware support.}} || rowspan=2 {{n/a}} || colspan=13 | v2 || colspan=2 | v1 || colspan=7 | v2
+|-
+| {{rh}} colspan=3 | [[Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)|BMI1]], [[AES_instruction_set|AES-NI]], [[CLMUL]], and [[F16C]]
+| colspan=13 {{ya}} || rowspan=2 {{n/a}} || colspan=9 rowspan=2 {{ya}}
+|-
+| {{rh}} colspan=3 | MOVBE || colspan=5 rowspan=2 {{n/a}} || rowspan=2 colspan=9 {{ya}}
+|-
+| {{rh}} colspan=3 | [[X86_virtualization#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)|AVIC]], [[Bit_Manipulation_Instruction_Sets#BMI2_(Bit_Manipulation_Instruction_Set_2))|BMI2]], [[RDRAND]], and MWAITX/MONITORX
+| colspan=4 {{n/a}} || colspan=5 {{ya}}
+|-
+| {{rh}} colspan=3 | [[AMD SME|SME]]{{efn|name=firmware|Requires firmware support.}}, [[TSME]]{{efn|name=firmware|Requires firmware support.}}, [[Intel_ADX|ADX]], [[Intel_SHA_extensions|SHA]], [[RDSEED]], [[Supervisor_Mode_Access_Prevention|SMAP]], [[Control_register#SMEP|SMEP]], XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing || colspan=7 {{n/a}} || colspan=7 {{ya}}
+| colspan=5 {{n/a}} || colspan=4 {{ya}}
+|-
+| {{rh}} colspan=3 | [[Second_Level_Address_Translation#Mode_Based_Execution_Control|GMET]], WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT || colspan=9 {{n/a}} || colspan=5 {{ya}}
+| colspan=8 {{n/a}} || {{ya}}
+|-
+| {{rh}} colspan=3 | [[Memory_protection#Protection_keys|MPK]], {{nowrap|[[VAES]]}} || colspan=10 {{n/a}} || colspan=4 {{ya}}
+| colspan=9 {{n/a}}
+|-
+| {{rh}} colspan=3 | [[Software Guard Extensions|SGX]] || colspan=14 {{n/a}} || colspan=9 {{n/a}}
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | [[Floating-point unit|FPUs]] per [[Multi-core processor|core]] || 1 || colspan=6 | 0.5 || colspan=7 | 1 || colspan=4 | 1 || 0.5 || colspan=4 | 1
+|-
+| {{rh}} colspan=3 | Pipes per FPU || colspan=14 | 2 || colspan=9 | 2
+|-
+| {{rh}} colspan=3 | FPU pipe width || colspan=9 | 128-bit || colspan=5 | 256-bit || 80-bit || colspan=7 | 128-bit || 256-bit
+|-
+| {{rh}} colspan=3 | CPU [[instruction set]] [[Single instruction, multiple data|SIMD]] level || [[SSE4a]]{{efn|name="sse4a"|No SSE4. No SSSE3.}} || colspan=4 | [[Advanced Vector Extensions|AVX]]
+| colspan=7 | [[Advanced Vector Extensions#Advanced_Vector_Extensions_2|AVX2]] || colspan=2 | [[AVX-512]] || [[SSSE3]] || colspan=3 | [[Advanced Vector Extensions|AVX]] || colspan=5 | [[Advanced Vector Extensions#Advanced_Vector_Extensions_2|AVX2]]
+|-
+| {{rh}} colspan=3 | [[3DNow!]] || [[3DNow!#3DNow_extensions|3DNow!+]] || colspan=13 {{n/a}}
+| colspan=9 {{n/a}}
+|-
+| {{rh}} colspan=3 | [[PREFETCHW|PREFETCH/PREFETCHW]] || colspan=14 {{ya}}
+| colspan=9 {{ya}}
+|-
+| {{rh}} colspan=3 | [[GFNI]] || colspan=12 {{n/a}} || colspan=2 {{ya}}
+| rowspan=2 colspan=9 {{n/a}}
+|-
+| {{rh}} colspan=3 | [[Advanced Matrix Extensions|AMX]] || colspan=14 {{n/a}}
+|-
+| {{rh}} colspan=3 | [[FMA4]], LWP, [[Bit_Manipulation_Instruction_Sets#TBM|TBM]], and [[XOP_instruction_set|XOP]] || rowspan=2 {{n/a}} || colspan=6 {{ya}} || colspan=7 {{n/a}}
+| rowspan=2 colspan=4 {{n/a}} || {{ya}} || colspan=4 {{n/a}}
+|-
+| {{rh}} colspan=3 | [[FMA3]] || colspan=13 {{ya}}
+| colspan=5 {{ya}}
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | [[AMD XDNA]] || colspan=13 {{n/a}} || {{ya}}
+| colspan=9 {{n/a}}
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | [[L1 cache|L1]] data cache per core (KiB) || 64 || colspan=4 | 16 || colspan=9 | 32 || colspan=9 | 32
+|-
+| {{rh}} colspan=3 | L1 data cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || 2 || colspan=4 | 4 || colspan=9 | 8 || colspan=9 | 8
+|-
+| {{rh}} colspan=3 | L1 instruction caches per [[Multi-core processor|core]] || 1 || colspan=6 | 0.5 || colspan=7 | 1
+| colspan=4 | 1 || 0.5 || colspan=4 | 1
+|-
+| {{rh}} colspan=3 | Max APU total L1 instruction cache (KiB) || 256 || colspan=2 | 128 || colspan=4 | 192 || colspan=5 | 256 || 512 || 256
+| colspan="2" | 64|| colspan="2" | 128
+|96
+|colspan=4| 128
+|-
+| {{rh}} colspan=3 | L1 instruction cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan=3 | 2 || colspan=4 | 3 || colspan=2 | 4 || colspan=5 | 8
+| colspan="4" | 2
+|3
+|colspan=3 | 4
+| 8
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | [[L2 cache]]s per [[Multi-core processor|core]] || 1 || colspan=6 | 0.5 || colspan=7 | 1 || colspan=4 | 1 || 0.5 || colspan=4 | 1
+|-
+| {{rh}} colspan=3 | Max APU total L2 cache (MiB) || colspan=5 | 4 || colspan=4 | 2 || colspan=3 | 4 || 16 || || 1 || colspan=3 | 2 || colspan=3 | 1 || colspan=2 | 2
+|-
+| {{rh}} colspan=3 | L2 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan=7 | 16 || colspan=7 | 8 || colspan=5 | 16 || colspan=4 | 8
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | Max on-die [[L3 cache]] per CCX (MiB) || colspan=7 rowspan=8 {{n/a}} || colspan=3 | 4 || colspan=2 | 16 || 32 || || colspan=6 rowspan=8 {{n/a}} || colspan=4 | 4
+|-
+| {{rh}} colspan="3" | Max 3D V-Cache per CCD (MiB) || colspan=5 {{n/a}} || 64 || {{n/a}} || colspan=4 {{n/a}}
+|-
+| {{rh}} colspan=3 | Max total in-CCD [[L3 cache]] per APU (MiB) || colspan=2 | 4 || 8 || colspan=2 | 16 || 64 || || colspan=4 | 4
+|-
+| {{rh}} colspan="3" | Max. total 3D V-Cache per APU (MiB) || colspan=5 {{n/a}} || 64 || {{n/a}} || colspan=4 {{n/a}}
+|-
+| {{rh}} colspan="3" | Max. board [[L3 cache]] per APU (MiB) || colspan=7 {{n/a}} || colspan=4 {{n/a}}
+|-
+| {{rh}} colspan=3 | Max total [[L3 cache]] per APU (MiB) || colspan=2 | 4 || 8 || colspan=2 | 16 || 128 || || colspan=4 | 4
+|-
+| {{rh}} colspan=3 | APU L3 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan=7 | 16 || colspan=4 | 16
+|-
+| {{rh}} colspan=3 | L3 cache scheme || colspan=7 | [[Victim cache|Victim]] || colspan=4 | [[Victim cache|Victim]]
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan="3" | Max. [[L4 cache]] || colspan="14" {{n/a}} || colspan=9 | n/a -->
+|-style="border-top:0.2em solid grey"
+| colspan=3 | Max stock [[Dynamic random-access memory|DRAM]] support || colspan=2 | DDR3-1866 || colspan=3 | DDR3-2133 || DDR3-2133, DDR4-2400 || DDR4-2400 || colspan=2 | DDR4-2933 || colspan=2 | DDR4-3200, LPDDR4-4266 || DDR5-4800, LPDDR5-6400 || DDR5-5200 || DDR5-5600, LPDDR5x-7500 || DDR3L-1333 || DDR3L-1600 || colspan=2 | DDR3L-1866 || DDR3-1866, DDR4-2400 || DDR4-2400 || DDR4-1600 || DDR4-3200 || LPDDR5-5500
+|-
+| colspan=3 | Max [[Dynamic random-access memory|DRAM]] channels per APU || colspan=14 | 2 || colspan=5 | 1 || 2 || 1 || colspan=2 | 2
+|-
+| colspan=3 | Max stock [[Dynamic random-access memory|DRAM]] [[Bandwidth (computing)|bandwidth]] (GB/s) per APU || colspan=2 | 29.866 || colspan=3 | 34.132 || colspan=2 | 38.400 || colspan=2 | 46.932 || colspan=2 | 68.256 || 102.400 || 83.200 || 120.000
+| 10.666 || 12.800 || colspan=2 | 14.933 || 19.200 || 38.400 || 12.800 || 51.200 || 88.000
+|-style="border-top:0.2em solid grey"
+| colspan=3 | GPU [[microarchitecture]] || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan=2 | [[TeraScale (microarchitecture)#TeraScale 3 "Northern Islands"-family|TeraScale 3 (VLIW4)]] || colspan=2 | [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]] || colspan=2 | [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]] || colspan=4 | [[Graphics Core Next#GCN 5th generation|GCN 5th gen]]<ref name="Vega codenames">{{cite book  |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |access-date=6 June 2017}}</ref> || colspan=2 | [[RDNA 2]] || [[RDNA 3]] || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan=3 | [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]] || [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]]<ref name="Vega codenames" /> || colspan=3 | [[Graphics Core Next#GCN 5th generation|GCN 5th gen]] || [[RDNA 2]]
+|- <!--
+| {{rh}} colspan=3 | GPU [[instruction set]] || colspan=3 | [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan=8 | [[Graphics Core Next#Instruction set|GCN instruction set]] || colspan=3 | [[RDNA (microarchitecture)#Instruction set|RDNA instruction set]] || [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan=7 | [[Graphics Core Next#Instruction set|GCN instruction set]] || [[RDNA (microarchitecture)#Instruction set|RDNA instruction set]]
+|-
+| {{rh}} colspan=3 | Max stock GPU base clock (MHz) || 600 || 800 || 844 || colspan=2 | 866 || colspan=2 | 1108 || 1250 || 1400 || colspan=2 | 2100 || 2400 || 400 ||
+| 538 || 600 || {{dunno}} || 847 || 900 || 1200 || 600 || 1300 || 1900
+|-
+| {{rh}} colspan=3 | Max stock GPU base [[GFLOPS]]{{efn|name="SFLOPS"}} || 480 || 614.4 || 648.1 || colspan=2 | 886.7 || colspan=2 | 1134.5 || 1760 || 1971.2 || colspan=2 | 2150.4 || 3686.4 || 102.4 ||
+| 86 || {{dunno}} || {{dunno}} || {{dunno}} || 345.6 || 460.8 || 230.4 || 1331.2 || 486.4
+|-style="border-top:0.2em solid grey"
+| rowspan=2 {{rh}} colspan=3 | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || Up to 400:20:8 || colspan=2 | Up to 384:24:6 || colspan=4 | Up to 512:32:8 || colspan=2 | Up to 704:44:16<ref>{{cite news |last1=Cutress |first1=Ian |title=Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm |url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3 |access-date=7 February 2018 |publisher=Anandtech |date=1 February 2018}}</ref> || colspan=2 | Up to 512:32:8 || 768:48:8 || 128:8:4 || || 80:8:4 || colspan=3 | 128:8:4 || Up to 192:12:8 || Up to 192:12:4 || 192:12:4 || Up to 512:?:? || 128:?:?
+|-
+| colspan=3 | IOMMUv1 || colspan=11 | [[Heterogeneous Memory Management|IOMMUv2]] || colspan=2 | IOMMUv1 || colspan=2 {{dunno}} || colspan=5 | IOMMUv2
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | Video decoder || colspan=3 | [[Unified Video Decoder#UVD 3|UVD 3.0]] || colspan=2 | [[Unified Video Decoder#UVD 4|UVD 4.2]] || colspan=2 | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan=2 colspan=2 | [[Video Core Next|VCN]] 1.0<ref>{{cite news |last1=Larabel |first1=Michael |title=Radeon VCN Encode Support Lands in Mesa 17.4 Git |url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands |access-date=20 November 2017 |publisher=Phoronix |date=17 November 2017}}</ref> || rowspan="2" | VCN 2.1<ref name="wccftechCezanne">{{cite web|last=|first=|date=Aug 12, 2021|title=AMD Ryzen 5000G ‘Cezanne’ APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package|url=https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/|access-date=August 25, 2021|website=wccftech|quote=}}</ref>
+| rowspan="2" | VCN 2.2<ref name="wccftechCezanne" /> || colspan=2 rowspan=2 | VCN 3.1 || rowspan=2 {{dunno}} || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || colspan=2 | [[Unified Video Decoder#UVD 4|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.2]] || rowspan=2 colspan=3 | [[Video Core Next|VCN 1.0]] || rowspan=2 | VCN 3.1
+|-
+| {{rh}} colspan=3 | Video encoder || {{n/a}} || colspan=2 | [[Video Coding Engine#VCE 1.0|VCE  1.0]] || colspan=2 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || {{n/a}} || colspan=3 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || [[Video Coding Engine#VCE 3.0|VCE 3.4]]
+|-
+| {{rh}} colspan=3 |AMD Fluid Motion
+| colspan=3 {{na}}
+| colspan=4 {{ya}}
+| colspan=7 {{na}}
+| colspan=2 {{na}}
+| colspan=3 {{ya}}
+| colspan=4 {{na}}
+|-
+| {{rh}} colspan=3 | GPU power saving || [[AMD PowerPlay|PowerPlay]] || colspan=13 | [[AMD PowerTune|PowerTune]] || [[AMD PowerPlay|PowerPlay]] || colspan=8 | [[AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |access-date=13 August 2016}}</ref>
+|-
+| {{rh}} colspan=3 | [[AMD TrueAudio|TrueAudio]] || colspan=3 rowspan=2 {{n/a}} || colspan=7 {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD's Kaveri architecture |publisher=Semi Accurate |access-date=6 July 2014}}</ref> || colspan=4 {{dunno}}
+| rowspan=2 {{n/a}} || colspan=8 {{ya}}
+|-
+| {{rh}} colspan=3 | [[FreeSync]] || colspan=11 style="background:#DFD" | 1<br>2
+| colspan=88 style="background:#DFD" | 1<br>2
+|-
+| {{rh}} colspan=3 | [[HDCP]]{{efn|name="DRM"}} || colspan=3 {{dunno}} || colspan=4 | 1.4 || colspan=4 | 2.2 || colspan=3 | 2.3 || {{dunno}} || colspan=4 | 1.4 || colspan=3 | 2.2 || 2.3
+|-
+| {{rh}} colspan=3 | [[PlayReady]]{{efn|name="DRM"}} || colspan=7 {{n/a}} || colspan=7 | 3.0 not yet || colspan=5 {{n/a}} || colspan=4 | 3.0 not yet
+|-
+| {{rh}} colspan=3 | [[AMD Eyefinity|Supported displays]]{{efn|To feed more than two displays, the additional panels must have native [[DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | access-date=8 December 2014}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan=4 | 2–4 || colspan=2 | 3 || colspan=2 | 3 (desktop)<br>4 (mobile, embedded) || colspan=5 | 4 || colspan=4 | 2 || 3 || 4 || || colspan=2 | 4
+|-style="border-top:0.2em solid grey"
+| {{rh}} colspan=3 | <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=26 November 2009 |access-date=16 January 2016 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |access-date=10 January 2016}}</ref> || colspan=6 {{ya}} || colspan=8 {{n/a}}
+| colspan=4 {{ya}} || colspan=5 {{n/a}}
+|-
+| {{rh}} colspan=3 | <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=16 September 2015 |last1=Deucher |first1=Alexander |access-date=16 January 2016}}</ref> || colspan=3 {{n/a}} || colspan=11 {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=17 November 2016}}</ref>
+| {{n/a}} || colspan=8 {{ya}}<ref name="amdgpu_1.2"/> -->
+|}
+<!--
+{{noteslist|refs=
+{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a [[Fused multiply–add|FMA]] operation.}}
+{{efn|name="drm"|DRM ([[Direct Rendering Manager]]) is a component of the Linux kernel. Support in this table refers to the most current version.}}
+{{efn|name="DRM"|To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.}}
+}}<noinclude>{{documentation|content=
+{{Template reference list}}
+== See also ==
+• Template:AMD x86 CPU features was deleted per oldid=1142398499#Template:AMD_x86_CPU_features
+* [[Template:AMD GPU features]]
+[[Category:AMD products| ]]
+[[Category:Computer hardware navigational boxes]]
+[[Category:Computer company templates]]
+[[Category:Templates that generate named references]]
+}}</noinclude>
+-->
 ==[[AMD]] Sockets (x86)==