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Socket S1g2 - AMD
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Socket S1g2
General Info
DesignerAMD
IntroductionJune 4, 2008 (launched)
MarketMobile
TDP35 W
Package
NameOPGA-638
TypeOrganic Micro Pin Grid Array
Contacts638
Dimension35.0 mm × 35.0 mm
Pitch1.27 mm
Socket
NameSocket S1g2
TypePGA

Socket S1g2 was the second socket for OPGA-638-packaged AMD mobile microprocessors with an integrated DDR2 memory controller, and the successor to Socket S1g1. It was superseded by Socket S1g3.

The main improvements of Socket S1g2 over S1g1 are support for HyperTransport generation 3.0 and separate power planes for each core and the northbridge, a power saving feature. S1g2 processors support dual plane platforms supplying the same voltage to both cores, but not a single plane supplying the northbridge as well.

Socket S1g2 was used in AMD's "Puma" mobile platform. All processors for Socket S1g2 are members of AMD's CPU Family 11h.

All revisions of Socket S1 have the same dimensions, however processors for Socket S1g2 appear to be electrically incompatible with Socket S1g1. Socket S1g2 and S1g3 have the same pinout, if processors for these sockets are exchangeable is unclear. Socket S1g2 processors will not work in Socket S1g4 systems, which use DDR3 memory, but S1g4 processors which support both DDR2 and DDR3 memory may be compatible with Socket S1g2 if the BIOS recognizes the CPU.

Features[edit]

  • 638-pin lidless micro pin grid array package, 1.27 mm pitch, 26 × 26 pins, 35 × 35 mm, organic substrate, C4 (flip chip) die attachment
  • 16 bit HyperTransport 3.0 interface up to 1800 MHz, 3600 MT/s, 7.2 GB/s in each direction
  • 2 × 64 bit DDR2 SDRAM interface up to 400 MHz, PC2-6400 (DDR2-800), 12.8 GB/s
    • Up to 2 unbuffered SO-DIMMs, no ECC support
    • JEDEC SSTL_1.8
  • Power Management
    • AMD PowerNow! technology
    • Up to 8 P-states; ACPI C1, C1E, C2, C3, S1, S3, S5
    • Triple power planes
    • HT link power management

Chipsets[edit]

  • AMD M780G, M780V
  • AMD 880M
  • AMD SB700, SB710, SB820 southbridge

Processors using Socket S1g2[edit]

  • AMD Turion X2 Ultra, codename "Griffin"
  • AMD Turion X2
  • AMD Athlon X2
  • AMD Sempron "Sable"
 List of all Socket S1g2-based Processors
ModelPriceProcessLaunchedµarchFamilyCoreCTFreqTurboTDP
Count: 0

Package Diagram[edit]

No data available. Dimensions should be similar to those of the OPGA-638 package shown on the Socket S1g1 page.

Socket Outline[edit]

Socket S1 diag.svg

Socket S1 limits as specified in AMD Publ. #31839. Depicted is Foxconn Interconnect Technology Part No. PZ6382A-284S-01F. All dimensions in millimeters.

Pin Map[edit]

Socket S1g2 pinmap.svg

For differences to other Socket S1 revisions see Socket S1g4.

Pin Description[edit]

Signal Description
ALERT_L Programmable pin that can indicate different events, including a SB-TSI interrupt
CLKIN_H/L 200 MHz Differential PLL Reference Clock
DBREQ_L, DBRDY Debug Request/Ready
HT_REF0, HT_REF1 HyperTransport Compensation Resistor to VSS, VLDT
KEY1, KEY2
L0_CADIN/OUT_H/L[15:0] HT Link 0 Differential Command/Address/Data Input/Output
L0_CLKIN/OUT_H/L[1:0] HT Link 0 Differential Clock Input/Output
L0_CTLIN_H/L[1:0] HT Link 0 Differential Control Input/Output
LDTREQ_L HT link is active or requested by a device input/output
LDTSTOP_L HT Stop Control Input for power management and link width and frequency change
MA0/MA1/MB0_CS_L[1:0], MB1_CS_L[0] DRAM Chip Select
MA0/MA1/MB0_ODT[1:0], MB1_ODT[0] DRAM Enable Pin for On Die Termination
MA/MB_ADD[15:0] DRAM Column/Row Address
MA/MB_BANK[2:0] DRAM Bank Address
MA/MB_CAS_L DRAM Column Address Strobe
MA/MB_CKE[1:0] DRAM Clock Enable
MA/MB_CLK_H/L[7/5/4/1] DRAM Differential Clock
MA/MB_DATA[63:0] DRAM Data Bus
MA/MB_DM[7:0] DRAM Data Mask
MA/MB_DQS_H/L[7:0] DRAM Differential Data Strobe
MA/MB_RAS_L DRAM Row Address Strobe
MA/MB_WE_L DRAM Write Enable
MEMHOT_L DRAM Thermal Protection input
M_VREF DRAM Interface Voltage Reference
M_ZP, M_ZN Compensation Resistor to VSS, VDDIO
PROCHOT_L Processor in HTC-active state input/output
PWROK Voltages and CLKIN have reached specified operation
RESET_L Processor Reset
RSVD Reserved
SIC, SID Sideband Temperature Sensor Interface (SB-TSI) Clock, Data
SVC, SVD Serial Voltage ID Interface Clock, Data
TCK, TDI, TDO, TMS, TRST_L JTAG interface
TEST* Test signal
THERMDA, THERMDC Thermal Diode Anode, Cathode
THERMTRIP_L Thermal Sensor Trip output
VDD0 Core 0 power supply
VDD0_FB_H/L Differential feedback to VDD0 regulator
VDD1 Core 1 power supply
VDD1_FB_H/L Differential feedback to VDD1 regulator
VDDA Filtered PLL supply voltage
VDDIO DRAM I/O ring power supply
VDDIO_FB_H/L Differential feedback to VDDIO regulator
VDDNB Northbridge power supply
VDDNB_FB_H/L Differential feedback to VDDNB regulator
VLDT_A/B HyperTransport I/O ring power supply
VSS Ground
VTT DRAM Termination voltage
VTT_SENSE VTT monitor pin

References[edit]

See also[edit]

Facts about "Socket S1g2 - AMD"
designerAMD +
first launchedJune 4, 2008 +
instance ofpackage +
market segmentMobile +
nameSocket S1g2 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +