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Difference between revisions of "3 nm lithography process"

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== Specifications ==
 
== Specifications ==
−
{{future information}}
+
 
 
{{finfet nodes comp
 
{{finfet nodes comp
 
<!-- Intel -->
 
<!-- Intel -->
 
  | process 1 fab          = [[Intel]]
 
  | process 1 fab          = [[Intel]]
−
  | process 1 name        = P1278 (CPU), P1279 (SoC)
+
  | process 1 name        = P1276 (CPU/Chipset)
−
  | process 1 date        = 2H 2023
+
  | process 1 date        = 2024
 
  | process 1 lith        = EUV
 
  | process 1 lith        = EUV
−
  | process 1 immersion    = &nbsp;
+
  | process 1 immersion    = Yes
−
  | process 1 exposure    = SE
+
  | process 1 exposure    = SE EUV+DUV SAPQ
 
  | process 1 wafer type  = Bulk
 
  | process 1 wafer type  = Bulk
 
  | process 1 wafer size  = 300 mm
 
  | process 1 wafer size  = 300 mm
 
  | process 1 transistor  = FinFET
 
  | process 1 transistor  = FinFET
 
  | process 1 volt        = &nbsp;
 
  | process 1 volt        = &nbsp;
−
  | process 1 delta from  = [[5 nm]] Δ
+
  | process 1 delta from  = [[4 nm]] Δ
−
  | process 1 fin pitch    = &nbsp;
+
  | process 1 fin pitch    = 30 nm
−
  | process 1 fin pitch Δ  = &nbsp;
+
  | process 1 fin pitch Δ  = 1.0x
 
  | process 1 fin width    = &nbsp;
 
  | process 1 fin width    = &nbsp;
−
  | process 1 fin width Δ  = &nbsp;
+
  | process 1 fin width Δ  = narrower
 
  | process 1 fin height  = &nbsp;
 
  | process 1 fin height  = &nbsp;
−
  | process 1 fin height Δ = &nbsp;
+
  | process 1 fin height Δ = taller
 
  | process 1 gate len    = &nbsp;
 
  | process 1 gate len    = &nbsp;
−
  | process 1 gate len Δ  = &nbsp;
+
  | process 1 gate len Δ  = 1.0x
 
  | process 1 cpp          = 50 nm
 
  | process 1 cpp          = 50 nm
−
  | process 1 cpp Δ        = &nbsp;
+
  | process 1 cpp Δ        = 1.0x
 
  | process 1 mmp          = 30 nm
 
  | process 1 mmp          = 30 nm
−
  | process 1 mmp Δ        = &nbsp;
+
  | process 1 mmp Δ        = 1.0x
−
  | process 1 sram hp      = &nbsp;
+
  | process 1 sram hp      = 0.0300 μm<sup>2</sup>
−
  | process 1 sram hp Δ    = &nbsp;
+
  | process 1 sram hp Δ    = 1.0x
−
  | process 1 sram hd      = &nbsp;
+
  | process 1 sram hd      = 0.0240 μm<sup>2</sup>
−
  | process 1 sram hd Δ    = &nbsp;
+
  | process 1 sram hd Δ    = 1.0x
 
  | process 1 sram lv      = &nbsp;
 
  | process 1 sram lv      = &nbsp;
 
  | process 1 sram lv Δ    = &nbsp;
 
  | process 1 sram lv Δ    = &nbsp;
Line 57: Line 57:
 
  | process 1 dram Δ      = &nbsp;
 
  | process 1 dram Δ      = &nbsp;
 
<!-- TSMC -->
 
<!-- TSMC -->
−
| process 2 fab          = [[TSMC]]
+
| process 2 fab          = [[TSMC]]
−
  | process 2 name        = N3(B), N3E <info>N3 Enhanced</info>, N3P, N3X
+
  | process 2 name        = N3(B)
−
  | process 2 date        = Q4 2022
+
  | process 2 date        = 2023
 
  | process 2 lith        = EUV
 
  | process 2 lith        = EUV
−
  | process 2 immersion    = &nbsp;
+
  | process 2 immersion    = Yes
−
  | process 2 exposure    = SE
+
  | process 2 exposure    = SALELE
 
  | process 2 wafer type  = Bulk
 
  | process 2 wafer type  = Bulk
 
  | process 2 wafer size  = 300 mm
 
  | process 2 wafer size  = 300 mm
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  | process 2 volt        = &nbsp;
 
  | process 2 volt        = &nbsp;
 
  | process 2 delta from  = [[5 nm]] Δ
 
  | process 2 delta from  = [[5 nm]] Δ
−
  | process 2 fin pitch    = &nbsp;
+
  | process 2 fin pitch    = 23 nm
−
  | process 2 fin pitch Δ  = &nbsp;
+
  | process 2 fin pitch Δ  = 0.82x
 
  | process 2 fin width    = &nbsp;
 
  | process 2 fin width    = &nbsp;
 
  | process 2 fin width Δ  = &nbsp;
 
  | process 2 fin width Δ  = &nbsp;
Line 76: Line 76:
 
  | process 2 gate len    = &nbsp;
 
  | process 2 gate len    = &nbsp;
 
  | process 2 gate len Δ  = &nbsp;
 
  | process 2 gate len Δ  = &nbsp;
−
  | process 2 cpp          = 45 nm (48 nm)
+
  | process 2 cpp          = 47 nm <!-- (after 4% optical bloat) -->
−
  | process 2 cpp Δ        = &nbsp;
+
  | process 2 cpp Δ        = 0.88x/<!-- (drawn) -->0.92x <!-- (actual) -->
 
  | process 2 mmp          = 23 nm
 
  | process 2 mmp          = 23 nm
−
  | process 2 mmp Δ        = &nbsp;
+
  | process 2 mmp Δ        = 0.82x
−
  | process 2 sram hp      = 0.0199 μm<sup>2</sup>
+
  | process 2 sram hp      = &nbsp;
 
  | process 2 sram hp Δ    = &nbsp;
 
  | process 2 sram hp Δ    = &nbsp;
−
  | process 2 sram hd      = 0.0210 μm<sup>2</sup>
+
  | process 2 sram hd      = 0.0199 μm<sup>2</sup>
−
  | process 2 sram hd Δ    = &nbsp;
+
  | process 2 sram hd Δ    = 0.95x
 
  | process 2 sram lv      = &nbsp;
 
  | process 2 sram lv      = &nbsp;
 
  | process 2 sram lv Δ    = &nbsp;
 
  | process 2 sram lv Δ    = &nbsp;
 
  | process 2 dram        = &nbsp;
 
  | process 2 dram        = &nbsp;
 
  | process 2 dram Δ      = &nbsp;
 
  | process 2 dram Δ      = &nbsp;
−
<!-- Samsung -->
+
  | process 3 fab          = [[TSMC]]
−
  | process 3 fab          = [[Samsung]]
+
  | process 3 name        = N3E <info>N3 Enhanced</info>, N3P, N3X
−
  | process 3 name        = 3GAE <info>3nm Gate All Around Early</info>, 3GAP <info>3nm Gate All Around Plus</info>
+
  | process 3 date        = 2024, 2025, 2026
−
  | process 3 date        = 2H 2022
 
 
  | process 3 lith        = EUV
 
  | process 3 lith        = EUV
−
  | process 3 immersion    = &nbsp;
+
  | process 3 immersion    = Yes
−
  | process 3 exposure    = SE
+
  | process 3 exposure    = SALELE
 
  | process 3 wafer type  = Bulk
 
  | process 3 wafer type  = Bulk
 
  | process 3 wafer size  = 300 mm
 
  | process 3 wafer size  = 300 mm
−
  | process 3 transistor  = GAAFET (MBCFET)
+
  | process 3 transistor  = FinFET
 
  | process 3 volt        = &nbsp;
 
  | process 3 volt        = &nbsp;
 
  | process 3 delta from  = [[5 nm]] Δ
 
  | process 3 delta from  = [[5 nm]] Δ
−
  | process 3 fin pitch    = &nbsp;
+
  | process 3 fin pitch    = 23 nm
−
  | process 3 fin pitch Δ  = &nbsp;
+
  | process 3 fin pitch Δ  = 0.82x
 
  | process 3 fin width    = &nbsp;
 
  | process 3 fin width    = &nbsp;
 
  | process 3 fin width Δ  = &nbsp;
 
  | process 3 fin width Δ  = &nbsp;
Line 108: Line 107:
 
  | process 3 gate len    = &nbsp;
 
  | process 3 gate len    = &nbsp;
 
  | process 3 gate len Δ  = &nbsp;
 
  | process 3 gate len Δ  = &nbsp;
−
  | process 3 cpp          = 40 nm
+
  | process 3 cpp          = 48 nm
−
  | process 3 cpp Δ        = &nbsp;
+
  | process 3 cpp Δ        = 0.94x
−
  | process 3 mmp          = 32 nm
+
  | process 3 mmp          = 23 nm
−
  | process 3 mmp Δ        = &nbsp;
+
  | process 3 mmp Δ        = 0.82x
 
  | process 3 sram hp      = &nbsp;
 
  | process 3 sram hp      = &nbsp;
 
  | process 3 sram hp Δ    = &nbsp;
 
  | process 3 sram hp Δ    = &nbsp;
−
  | process 3 sram hd      = &nbsp;
+
  | process 3 sram hd      = 0.0210 μm<sup>2</sup>
−
  | process 3 sram hd Δ    = &nbsp;
+
  | process 3 sram hd Δ    = 1.0x
 
  | process 3 sram lv      = &nbsp;
 
  | process 3 sram lv      = &nbsp;
 
  | process 3 sram lv Δ    = &nbsp;
 
  | process 3 sram lv Δ    = &nbsp;
 
  | process 3 dram        = &nbsp;
 
  | process 3 dram        = &nbsp;
−
  | process 3 dram Δ      = &nbsp;<br>.
+
  | process 3 dram Δ      = &nbsp;
 +
<!-- Samsung -->
 +
| process 4 fab          = [[Samsung]]
 +
| process 4 name        = SF3E <info>3nm Gate All Around Early</info>, SF3 <info>3nm Gate All Around Plus</info>
 +
| process 4 date        = 2024
 +
| process 4 lith        = EUV
 +
| process 4 immersion    = Yes
 +
| process 4 exposure    = SALELE
 +
| process 4 wafer type  = Bulk
 +
| process 4 wafer size  = 300 mm
 +
| process 4 transistor  = GAAFET (MBCFET)
 +
| process 4 volt        = &nbsp;
 +
| process 4 delta from  = [[5 nm]] Δ
 +
| process 4 fin pitch    = &nbsp;
 +
| process 4 fin pitch Δ  = &nbsp;
 +
| process 4 fin width    = &nbsp;
 +
| process 4 fin width Δ  = &nbsp;
 +
| process 4 fin height  = &nbsp;
 +
| process 4 fin height Δ = &nbsp;
 +
| process 4 gate len    = &nbsp;
 +
| process 4 gate len Δ  = &nbsp;
 +
| process 4 cpp          = 48 nm
 +
| process 4 cpp Δ        = 1.0x
 +
| process 4 mmp          = 28 nm
 +
| process 4 mmp Δ        = 1.0x
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = &nbsp;
 +
| process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;<br>.
 
}}
 
}}
 +
  
 
=== 3 nm process nodes ===
 
=== 3 nm process nodes ===
 
{{see also|Intel 7|Intel 4|Intel 18A}}
 
{{see also|Intel 7|Intel 4|Intel 18A}}
−
{| class="wikitable" style="text-align:center"
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
 
!
 
!
−
! colspan=2 | [[Samsung]] <ref>{{cite book |url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ |title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements |website=WikiChip Fuse |date=5 July 2022}}</ref>
+
! colspan=2 | [[Samsung]] <ref>{{cite book |url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ |title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements |website=WikiChip Fuse |date=5 July 2022}}</ref><ref>{{cite book |url=https://ieeexplore.ieee.org/abstract/document/10185353 |title=https://ieeexplore.ieee.org/abstract/document/10185353 |website=IEEEexplore |date=16 June 2023}}</ref>
−
! colspan=4 | [[TSMC]] <ref>{{cite book |url=https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/ |title=TSMC N3, and Challenges Ahead |date=27 May 2023}}</ref>
+
! colspan=4 | [[TSMC]] <ref>{{cite book |url=https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/ |title=TSMC N3, and Challenges Ahead |date=27 May 2023}}</ref><ref>{{cite book |url=https://www-prod.techinsights.com/blog/apple-apl1v02-a17-pro-processor-tsmc-3-nm-finfet-process-digital-floorplan-analysis?utm_source=direct&utm_medium=website |title=Apple APL1V02 A17 Pro Processor TSMC 3 nm FinFET Process Digital Floorplan Analysis |date=27 Dec 2023}}</ref><ref>{{cite book |url=https://www.techinsights.com/blog/introducing-tsmc-n3e-power-behind-apples-m4-soc?utm_source=direct&utm_medium=website |title=Introducing TSMC N3E |date=15 April 2024}}</ref>
−
! [[Intel]] <ref>{{cite book |title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A |url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros |date=27 July 2021 |website=AnandTech}}</ref>
+
! [[Intel]] <ref>{{cite book |title=Intel Delivers Leading-Edge Foundry Node with Intel 3 Technology; on Path Back to Process Leadership |url=https://community.intel.com/t5/Blogs/Intel-Foundry/Systems-Foundry-for-the-AI-Era/Intel-Delivers-Leading-Edge-Foundry-Node-with-Intel-3-Technology/post/1607454 |date=18 June 2024 |website=community.intel.com}}</ref>
 
|-
 
|-
 
! Process name
 
! Process name
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| 2022 H1 risk <br>production <br>2022 H2 <br>production <br>2022 shipping  
 
| 2022 H1 risk <br>production <br>2022 H2 <br>production <br>2022 shipping  
 
| 2024 Q1 risk <br>production <br>2024 H2 <br>production
 
| 2024 Q1 risk <br>production <br>2024 H2 <br>production
−
| 2022 H1 risk <br>production <br>2022 H2 volume <br>production <br>2023 H1 shipping
+
| 2022 <br>risk production <br>2023<br>production
−
| 2023 H2 <br>production
+
| 2024 <br>
−
| 2024 H2 <br>production
+
| 2025 <br>
−
| 2025 H2 <br>production
+
| 2026 <br>
−
| 2024 H1 product <br>manufacturing <br>2024 H2 shipping
+
| 2024
 
|-
 
|-
 
|}
 
|}

Latest revision as of 18:15, 27 June 2025

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing

process following the 5 nm process node.

Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and

does not represent any geometry of the transistor.

Industry[edit]

Intel[edit]

P1278 Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H 2024/2025 timeframe.

TSMC[edit]

N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to

30% power reduction at the same speed as compared with N5 technology (According to TSMCs website).

If this holds true we could see 300+ MT/mm2.

Samsung[edit]

On May 24, 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET

(MBCFET), an extension of a Gate-all-around (GAA) FET.

This is planned for somewhere after the 5 nm node but the exact timeline or specification is currently unknown.

Specifications[edit]

 
Process Name
1st Production
Litho-
graphy 		Lithography
Immersion
Exposure
Wafer Type
Size
Tran-
sistor 		Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM
bitcell 		High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM
bitcell 		eDRAM
Intel TSMC TSMC Samsung
P1276 (CPU/Chipset) N3(B) N3E
N3 Enhanced
, N3P, N3X		 SF3E
3nm Gate All Around Early
, SF3
3nm Gate All Around Plus
2024 2023 2024, 2025, 2026 2024
EUV EUV EUV EUV
Yes Yes Yes Yes
SE EUV+DUV SAPQ SALELE SALELE SALELE
Bulk Bulk Bulk Bulk
300 mm 300 mm 300 mm 300 mm
FinFET FinFET FinFET GAAFET (MBCFET)
       
Value 4 nm Δ Value 5 nm Δ Value 5 nm Δ Value 5 nm Δ
30 nm 1.0x 23 nm 0.82x 23 nm 0.82x    
  narrower            
  taller            
  1.0x            
50 nm 1.0x 47 nm 0.88x/0.92x 48 nm 0.94x 48 nm 1.0x
30 nm 1.0x 23 nm 0.82x 23 nm 0.82x 28 nm 1.0x
0.0300 μm2 1.0x            
0.0240 μm2 1.0x 0.0199 μm2 0.95x 0.0210 μm2 1.0x    
               
               
.


3 nm process nodes[edit]

See also: Intel 7, Intel 4, and Intel 18A
Samsung [1][2] TSMC [3][4][5] Intel [6]
Process name 3GAE (SF3E) 3GAP (SF3) N3 (N3B) N3E N3P N3X Intel 3
Transistor type GAAFET (MBCFET) FinFET
Transistor density
(MTr/mm2) 		150 190 197 216 224 -
Transistor gate
pitch (nm) 		40 - 45 48 - - 50
Interconnect
pitch (nm) 		32 - - 23 - - 30
SRAM bit-cell
size (μm2) 		- - 0.0199 0.021 - - -
Release status 2022 H1 risk
production
2022 H2
production
2022 shipping 		2024 Q1 risk
production
2024 H2
production 		2022
risk production
2023
production 		2024
2025
2026
2024


2 nm process nodes[edit]

Samsung TSMC Intel
Process name SF2 SF2P SF2X SF2Z N2 N2P N2X 20A 18A
Transistor type MBCFET GAAFET RibbonFET
Transistor density (MTr/mm2) 231 - - - 313 - - - 238
Transistor gate
pitch (nm) 		- - - - - - - - -
Interconnect
pitch (nm) 		- - - - - - - - -
SRAM bit-cell
size (μm2) 		- - - - 0.0175 μm² - - - 0.021 μm²
Release status 2025 volume production 2026 volume production 2026 volume production 2027 volume production 2024 H2 risk production
2025 H2 volume production 		2026 H2
volume production 		2026 H2
volume production 		2024 H1 risk production
2024 volume production
Canceled 2024 		2024 H2 risk production
2025 H1 production

3 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

3 nm Microarchitectures[edit]

4 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017
  • ↑ (5 July 2022) Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements.
  • ↑ (16 June 2023) https://ieeexplore.ieee.org/abstract/document/10185353.
  • ↑ (27 May 2023) TSMC N3, and Challenges Ahead.
  • ↑ (27 Dec 2023) Apple APL1V02 A17 Pro Processor TSMC 3 nm FinFET Process Digital Floorplan Analysis.
  • ↑ (15 April 2024) Introducing TSMC N3E.
  • ↑ (18 June 2024) Intel Delivers Leading-Edge Foundry Node with Intel 3 Technology; on Path Back to Process Leadership.
    • Retrieved from "https://en.wikichip.org/w/index.php?title=3_nm_lithography_process&oldid=103500"