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Semiconductor lithography processes technology

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The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. Mass production of integrated circuit fabricated using a 7 nm process begun in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the 5 nm node.

The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Overview

First introduced by the major foundries around the 2018-19 timeframe, the 7-nanometer process technology is characterized by its use of FinFET transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, quad patterning had to be utilized for some layers. This process was introduced just as EUV Lithography became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel 10 nm process is comparable to the foundry 7-nanometer node.

Density

In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-105 million transistors per square millimeter based on WikiChip's own analysis.

Industry

Only three companies are currently planning or developing a 5-nanometer node: Intel, TSMC, and Samsung.

Intel

P1276

Intel's 7-nanometer process, P1276, will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.

Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 transistors per square millimeter.

TSMC

TSMC started mass production of its 7-nanometer N7 node in April 2018. TSMC considers its 7-nanometer node a full node shrink over its 16-nanometer. Although TSMC has released a 10-nanometer node the year prior, the company considered its 10 nm to be a short-lived node and was intended to serve as a learning node on its way to 7. In early 2019 TSMC introduced the second version of its N7 process called N7P which provides additional performance enhancements.

N7

TSMC original 7-nanometer N7 process was introduced in April 2018. Compared to its own 16-nanometer technology, TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power. N7 largely builds on all prior FinFET processes the company has had prevously. To that end, this is a fourth-generation FinFET, fifth-generation HKMG, gate-last, dual gate oxide process.

W_eff for TSMC 16, 10, and 7 nm.

For N7, TSMC continued to use deep ultraviolet (DUV) 193 nm ArF Immersion lithography. The limitations of i193 dictated some of the design rules for the process. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the SADP point. Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point. The design rules for N7 are shown below.

Elements distribution of Apple's A12 SoC by MSS Corp. Cobalt contacts can be seen.

The transistor profile has been enhanced as well. Like Intel's 10 nm process, TSMC introduced cobalt fill at the trench contacts, replacing the tungsten contact. This has the effect of reducing the resistance in that area by 50%. Some of the area scaling and cost benefits were achieved through fin pitch/height scaling. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and subthreshold slope (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I device delay is still better because the intrinsic capacitance like the Cgate and Cov still scale with Ieff.

Another way to visualize the effect of the width and height scaling is through the effective width. In the graph shown on the left, we plotted the effective width from TSMC 16 nanometer to the current 7-nanometer node. Compared to N16, N7 has over twice the effective channel width.

Different multi-Vt devices were developed for this process with a Vt range of around 200 mV.

TSMC 7-nanometer comes in two variations - low power and high performance. Those cells are 240 nm and 300 nm tall respectively.

Qualcomm's Snapdragon 855 self-reported Ieff difference between the HD and HP cells.

Qualcomm reported that on its own SoC (Snapdragon 855), the high-performance cells deliver around 10-13% higher effective drive current (Ieff), albeit at the cost of being slightly leakier transistors. Based on WikiChip's own analysis, the dense cells come at around 91.2 MTr/mm² while the less dense, high-performance cells, are calculated at around 65 MTr/mm².

N7P

Samsung

Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development. On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.

7LPE

7LPP

GlobalFoundries

• Note: As of august 2018 GlobalFoundries has announced they will suspend further development of their 7nm, 5nm and 3nm process.

On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of EUV, the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.

The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips.

7LP

7HPC

7 nm Microprocessors

• PEZY
  • PEZY-SC3
• MediaTek
  • Helio M70
• Apple
  • A12
  • A12X
  • A13
• HiSilicon (Huawei)
  • 990
  • 980
  • 810
• Snapdragon (Qualcomm)
  • 855

This list is incomplete; you can help by expanding it.

7 nm Microarchitectures

• AMD
  • Vega 20
  • Navi
  • Zen 2
  • Zen 3
• Ampere
  • Quicksilver
• Esperanto
  • ET-Minion
  • ET-Maxion
• Intel
  • Granite Rapids
  • Meteor Lake
  • Knights Peak

See also

• Intel process technology history

References