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Difference between revisions of "7 nm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
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The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of [[integrated circuit]]s using a 7 nm process has begun in 2018. This technology will be replaced by the [[5 nm lithography process|5 nm process]] around 2020/21.
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The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process begun in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]].
  
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== Industry ==
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The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
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Only three semiconductor foundries are currently working on a 7nm process: [[Intel]], [[Samsung]] and [[TSMC]].
+
 
 +
== Overview ==
 +
First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel [[10 nm process]] is comparable to the foundry 7-nanometer node.
 +
 
 +
=== Density ===
 +
In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-105 million [[transistors per square millimeter]] based on WikiChip's own analysis.
  
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{{future information}}
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:[[File:7nm densities.svg|600px]]
  
 +
== Industry ==
 +
Only three companies are currently planning or developing a 5-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]].
  
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{{finfet nodes comp
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{{node comp|node=7 nm}}
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<!-- Intel -->
 
−
| process 1 fab          = [[Intel]]
 
−
| process 1 name        = P1276 (CPU), P1277 (SoC)
 
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| process 1 date        = &nbsp;
 
−
| process 1 lith        = EUV
 
−
| process 1 immersion    = &nbsp;
 
−
| process 1 exposure    = &nbsp;
 
−
| process 1 wafer type  = Bulk
 
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| process 1 wafer size  = 300 mm
 
−
| process 1 transistor  = &nbsp;
 
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| process 1 volt        = &nbsp;
 
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| process 1 delta from  = [[10 nm]] Δ
 
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| process 1 fin pitch    = &nbsp;
 
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| process 1 fin pitch Δ  = &nbsp;
 
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| process 1 fin width    = &nbsp;
 
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| process 1 fin width Δ  = &nbsp;
 
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| process 1 fin height  = &nbsp;
 
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| process 1 fin height Δ = &nbsp;
 
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| process 1 gate len    = &nbsp;
 
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| process 1 gate len Δ  = &nbsp;
 
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| process 1 cpp          = &nbsp;
 
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| process 1 cpp Δ        = &nbsp;
 
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| process 1 mmp          = &nbsp;
 
−
| process 1 mmp Δ        = &nbsp;
 
−
| process 1 sram hp      = &nbsp;
 
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| process 1 sram hp Δ    = &nbsp;
 
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| process 1 sram hd      = &nbsp;
 
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| process 1 sram hd Δ    = &nbsp;
 
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| process 1 sram lv      = &nbsp;
 
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| process 1 sram lv Δ    = &nbsp;
 
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| process 1 dram        = &nbsp;
 
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| process 1 dram Δ      = &nbsp;
 
−
<!-- TSMC -->
 
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| process 2 fab          = [[TSMC]]
 
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| process 2 name        = 7FF, 7FF+<info>will use EUVL instead of immersion lithography</info>, 7HPC
 
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| process 2 date        = Q1, 2018
 
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| process 2 lith        = 193 nm
 
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| process 2 immersion    = Yes
 
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| process 2 exposure    = SAQP
 
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| process 2 wafer type  = Bulk
 
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| process 2 wafer size  = 300 mm
 
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| process 2 transistor  = FinFET
 
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| process 2 volt        = 0.70 V
 
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| process 2 delta from  = [[10 nm]] Δ
 
−
| process 2 fin pitch    = &nbsp;
 
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| process 2 fin pitch Δ  = &nbsp;
 
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| process 2 fin width    = 6 nm
 
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| process 2 fin width Δ  = 1.00x
 
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| process 2 fin height  = 52 nm
 
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| process 2 fin height Δ = 1.24x
 
−
| process 2 gate len    = &nbsp;
 
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| process 2 gate len Δ  = &nbsp;
 
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| process 2 cpp          = 55 nm
 
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| process 2 cpp Δ        = 0.84x
 
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| process 2 mmp          = 40 nm
 
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| process 2 mmp Δ        = 0.95x
 
−
| process 2 sram hp      = &nbsp;
 
−
| process 2 sram hp Δ    = &nbsp;
 
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| process 2 sram hd      = 0.027 µm²
 
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| process 2 sram hd Δ    = 0.64x
 
−
| process 2 sram lv      = &nbsp;
 
−
| process 2 sram lv Δ    = &nbsp;
 
−
| process 2 dram        = &nbsp;
 
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| process 2 dram Δ      = &nbsp;
 
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<!-- GlobalFoundries -->
 
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| process 3 fab          = [[GlobalFoundries]]
 
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| process 3 name        = 7LP<info>7nm Leading Performance</info>
 
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| process 3 date        = cancelled
 
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| process 3 lith        = 193 nm
 
−
| process 3 immersion    = Yes
 
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| process 3 exposure    = SAQP
 
−
| process 3 wafer type  = Bulk
 
−
| process 3 wafer size  = 300 mm
 
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| process 3 transistor  = FinFET
 
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| process 3 volt        = 0.70 V
 
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| process 3 delta from  = [[14 nm]] Δ
 
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| process 3 fin pitch    = 30 nm
 
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| process 3 fin pitch Δ  = 0.63x
 
−
| process 3 fin width    = &nbsp;
 
−
| process 3 fin width Δ  = &nbsp;
 
−
| process 3 fin height  = &nbsp;
 
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| process 3 fin height Δ = &nbsp;
 
−
| process 3 gate len    = &nbsp;
 
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| process 3 gate len Δ  = &nbsp;
 
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| process 3 cpp          = 56 nm
 
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| process 3 cpp Δ        = 0.72x
 
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| process 3 mmp          = 40 nm
 
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| process 3 mmp Δ        = 0.63x
 
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| process 3 sram hp      = 0.0353 µm²
 
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| process 3 sram hp Δ    = 0.44x
 
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| process 3 sram hd      = 0.0269 µm²
 
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| process 3 sram hd Δ    = 0.42x
 
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| process 3 sram lv      = &nbsp;
 
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| process 3 sram lv Δ    = &nbsp;
 
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| process 3 dram        = &nbsp;
 
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| process 3 dram Δ      = &nbsp;
 
−
<!-- Samsung -->
 
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| process 4 fab          = [[Samsung]]
 
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| process 4 name        = 7LPE<info>7 nm Low Power Early</info>
 
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| process 4 date        = 2019
 
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| process 4 lith        = EUV
 
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| process 4 immersion    = &nbsp;
 
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| process 4 exposure    = SE
 
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| process 4 wafer type  = Bulk
 
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| process 4 wafer size  = 300 mm
 
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| process 4 transistor  = FinFET
 
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| process 4 volt        = &nbsp;
 
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| process 4 delta from  = [[10 nm]] Δ
 
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| process 4 fin pitch    = &nbsp;
 
−
| process 4 fin pitch Δ  = &nbsp;
 
−
| process 4 fin width    = &nbsp;
 
−
| process 4 fin width Δ  = &nbsp;
 
−
| process 4 fin height  = &nbsp;
 
−
| process 4 fin height Δ = &nbsp;
 
−
| process 4 gate len    = &nbsp;
 
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| process 4 gate len Δ  = &nbsp;
 
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| process 4 cpp          = 54 nm
 
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| process 4 cpp Δ        = 0.79x
 
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| process 4 mmp          = 36 nm
 
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| process 4 mmp Δ        = 0.7x
 
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| process 4 sram hp      = &nbsp;
 
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| process 4 sram hp Δ    = &nbsp;
 
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| process 4 sram hd      = 0.0260 µm²
 
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| process 4 sram hd Δ    = 0.65x
 
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| process 4 sram lv      = &nbsp;
 
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| process 4 sram lv Δ    = &nbsp;
 
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| process 4 dram        = &nbsp;
 
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| process 4 dram Δ      = &nbsp;
 
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<!-- Common Platform -->
 
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| process 5 fab          = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper
 
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| process 5 name        = &nbsp;
 
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| process 5 date        = &nbsp;
 
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| process 5 lith        = EUV
 
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| process 5 immersion    = &nbsp;
 
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| process 5 exposure    = SE
 
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| process 5 wafer type  = Bulk
 
−
| process 5 wafer size  = 300 mm
 
−
| process 5 transistor  = FinFET
 
−
| process 5 volt        = &nbsp;
 
−
| process 5 delta from  = [[10 nm]] Δ
 
−
| process 5 fin pitch    = &nbsp;
 
−
| process 5 fin pitch Δ  = &nbsp;
 
−
| process 5 fin width    = &nbsp;
 
−
| process 5 fin width Δ  = &nbsp;
 
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| process 5 fin height  = &nbsp;
 
−
| process 5 fin height Δ = &nbsp;
 
−
| process 5 gate len    = &nbsp;
 
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| process 5 gate len Δ  = &nbsp;
 
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| process 5 cpp          = 48 nm
 
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| process 5 cpp Δ        = 0.75x
 
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| process 5 mmp          = 36 nm
 
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| process 5 mmp Δ        = 0.75x
 
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| process 5 sram hp      = &nbsp;
 
−
| process 5 sram hp Δ    = &nbsp;
 
−
| process 5 sram hd      = &nbsp;
 
−
| process 5 sram hd Δ    = &nbsp;
 
−
| process 5 sram lv      = &nbsp;
 
−
| process 5 sram lv Δ    = &nbsp;
 
−
| process 5 dram        = &nbsp;
 
−
| process 5 dram Δ      = &nbsp;
 
−
}}
 
  
 
=== Intel ===
 
=== Intel ===
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* '''Note:''' For the most part, foundries' 7nm process is competing against [[10_nm_lithography_process#Intel|Intel's 10nm process]], not their 7nm.
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==== P1276 ====
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Intel's 7-nanometer process, '''P1276''', will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.
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On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017 Mark Bohr, Intel's Senior Fellow and Director of Process Architecture and Integration, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the [[5 nm]] and [[3 nm]] nodes. Details of their 7 nm node have not been disclosed yet. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June.
 
  
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=== GlobalFoundries ===
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Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 [[transistors per square millimeter]].
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* '''Note:'''  As of august 2018 GlobalFoundries has announced they will suspend further development of their 7nm, 5nm and 3nm process.
 
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[[File:globalfoundries interconnect 7nm.jpg|right|350px]]
 
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On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.
 
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The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips.
 
  
 
=== TSMC ===
 
=== TSMC ===
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[[File:7nm tsmc.jpeg|right|200px]]
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==== N7 ====
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In ISSCC 2017, the memory group at [[TSMC]] detailed their test 256 Mib SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using SAQP. The over die is 0.34x the size of their [[16 nm process]] version. TSMC's 7nm process density is 1.6X compared to their 10nm process. Minimum metal pitch is 40 nm, as reported at IEDM 2016. TSMC claims their 7nm process will deliver a 20% performance improvement and a 40% reduction in power consumption.
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==== N7P ====
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=== Samsung ===
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The 7nm node will come in two variants, one optimized for mobile applications and a second one optimized for High Performance applications.
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==== 7LPE ====
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TSMC plans to introduce a second improved process called 7nm+ a year later, which will introduce some layers processed with EUVL. This will improve yields and reduce fab cycle times. The 7nm+ process will deliver improved power consumption and between 15-20% area scaling over their first generation 7nm process.
+
==== 7LPP ====
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+
=== GlobalFoundries ===
−
{| class="collapsible collapsed wikitable"
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==== 7LP ====
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|-
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==== 7HPC ====
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! colspan="2" | TSMC 256 Mib SRAM demo 7 nm wafer
 
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|-
 
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|
 
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<table class="wikitable">
 
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<tr><th>Technology</th><td>7 nm HK-MG FinFET</td></tr>
 
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<tr><th>Metal scheme</th><td>1 Poly  / 7 Metal</td></tr>
 
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<tr><th>Supply voltage</th><td>0.75 V (core)<br>1.8 V (i/o)</td></tr>
 
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<tr><th>Bit cell size</th><td>0.027 µm²</td></tr>
 
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<tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr>
 
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<tr><th>Capacity</th><td>256 Mib</td></tr>
 
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<tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
 
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<tr><th>Die Size</th><td>5903 µm x 7223 µm = 42.64 mm²</td></tr>
 
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</table>
 
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| [[File:tsmc 7nm SRAM block.png]]
 
−
|}
 
−
 
 
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=== Samsung===
 
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Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development.
 
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On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.
 
  
 
== 7 nm Microprocessors==
 
== 7 nm Microprocessors==
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== See also ==
 
== See also ==
−
 
 
* {{intel|process|Intel process technology history}}
 
* {{intel|process|Intel process technology history}}
  
 
== References ==
 
== References ==
−
* Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
 
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* Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016.
 
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* Samsung/GlobalFoundries, [[IEEE]] [[International Electron Devices Meeting]] (IEDM) 2016
 
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[[category:lithography]]
 

Revision as of 23:53, 29 December 2019

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. Mass production of integrated circuit fabricated using a 7 nm process begun in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the 5 nm node.

The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Overview

First introduced by the major foundries around the 2018-19 timeframe, the 7-nanometer process technology is characterized by its use of FinFET transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, quad patterning had to be utilized for some layers. This process was introduced just as EUV Lithography became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel 10 nm process is comparable to the foundry 7-nanometer node.

Density

In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-105 million transistors per square millimeter based on WikiChip's own analysis.

7nm densities.svg

Industry

Only three companies are currently planning or developing a 5-nanometer node: Intel, TSMC, and Samsung.

 IntelTSMCSamsungGlobalFoundries
ProcessP1276 (CPU), P1277 (SoC)N7, N7P, N7+7LPE, 7LPP7LP, 7HP
Production2021April 2018April 2019Cancelled
LithoLithographyEUVDUV ⇒ EUVEUVDUV ⇒ EUV
Immersion
Exposure		SADP ⇒ SE (EUV)
                DP (193i)		SE (EUV)
DP (193i)		SADP ⇒ SE (EUV)
                DP (193i)
WaferTypeBulk
Size300 mm
xTorTypeFinFET
Voltage
 Value10 nm ΔValue10 nm ΔValue10 nm ΔValue14 nm Δ
FinPitch30 nm0.83x27 nm0.64x30 nm0.625x
Width6 nm1.00x
Height52 nm1.24x
Gate Length (Lg)8/10 nm
Contacted Gate Pitch (CPP)64 nm (HP)
57 nm (HD)
0.82x		60 nm (HP)
54 nm (HD)
0.79x		56 nm0.72x
Minimum Metal Pitch (MMP)40 nm0.95x36 nm0.75x40 nm0.625x
SRAMHigh-Perf (HP)0.032 µm²0.65x0.0353 µm²0.44x
High-Density (HD)0.027 µm²0.64x0.026 µm²0.65x0.0269 µm²0.42x
Low-Voltage (LV)

Intel

P1276

Intel's 7-nanometer process, P1276, will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.

Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 transistors per square millimeter.

TSMC

N7

N7P

Samsung

7LPE

7LPP

GlobalFoundries

7LP

7HPC

7 nm Microprocessors

This list is incomplete; you can help by expanding it.

7 nm Microarchitectures

See also

References

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