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| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
| process 1 transistor = FinFET | | process 1 transistor = FinFET | ||
− | | process 1 volt = | + | | process 1 volt = 0.70 V |
| process 1 delta from = [[14 nm]] Δ | | process 1 delta from = [[14 nm]] Δ | ||
| process 1 fin pitch = 34 nm | | process 1 fin pitch = 34 nm | ||
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| process 3 wafer size = 300 mm | | process 3 wafer size = 300 mm | ||
| process 3 transistor = FinFET | | process 3 transistor = FinFET | ||
− | | process 3 volt = | + | | process 3 volt = 0.75 V |
| process 3 delta from = [[14 nm]] Δ | | process 3 delta from = [[14 nm]] Δ | ||
| process 3 fin pitch = | | process 3 fin pitch = | ||
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| process 4 wafer size = 300 mm | | process 4 wafer size = 300 mm | ||
| process 4 transistor = FinFET | | process 4 transistor = FinFET | ||
− | | process 4 volt = | + | | process 4 volt = 0.75 V |
| process 4 delta from = [[14 nm]] Δ | | process 4 delta from = [[14 nm]] Δ | ||
| process 4 fin pitch = | | process 4 fin pitch = |
Revision as of 13:25, 9 June 2017
The 10 nanometer (10 nm) lithography process is a semiconductor manufacturing process node serving as shrink from the 14 nm process. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 10 nm node is currently being introduced and is set to get replaced by the 7 nm process in 2019.
Contents
Industry
At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: Intel, Samsung, and TSMC.
Due to marketing names the transistor sizes vary considerably between leading manufactures. For example, Intel's 10nm process is denser and smaller than TSMC's 7 nm process while Samsung's 10 nm process is more similar to Intel's 14 nm process (e.g., a metal pitch just 1 nanometer shorter).
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Intel | TSMC | Samsung | Common Platform Alliance The Common Platform Alliance is a joint collaboration between IBM, Samsung, GlobalFoundries, STMicroelectronics, UMC Paper
| ||||
---|---|---|---|---|---|---|---|
P1274 (CPU) / P1275 (SoC) | 10LPE 1st generation; 10 nm Low Power Early , 10LPP2nd generation; 10 nm Low Power Performance , 10LPU3rd generation; 10 nm Low Power Ultimate |
||||||
2017 | 2017 | 2017 | |||||
193 nm | 193 nm | 193 nm | 193 nm | ||||
Yes | Yes | Yes | Yes | ||||
SAQP | LELELE | SADP | |||||
Bulk | Bulk | Bulk | Bulk/SOI | ||||
300 mm | 300 mm | 300 mm | 300 mm | ||||
FinFET | FinFET | FinFET | FinFET | ||||
0.70 V | 0.75 V | 0.75 V | |||||
Value | 14 nm Δ | Value | 16 nm Δ | Value | 14 nm Δ | Value | 14 nm Δ |
34 nm | 0.81x | ||||||
53 nm | 1.26x | ||||||
20 nm | |||||||
54 nm | 0.77x | 64 nm | 0.71x | 68 nm | 0.87x | 64 nm | 0.80x |
36 nm | 0.69x | 42 nm | 0.66x | 51 nm | 0.80x | 48 nm | 0.75x |
0.0441 µm² | 0.62x | 0.049 µm² | 0.61x | ||||
0.0312 µm² | 0.62x | 0.042 µm² | 0.57x | 0.040 µm² | 0.63x | 0.053 µm² | 0.65x |
0.0367 µm² | 0.62x | ||||||
Intel
- See also: Intel's Process Technology History
Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) with production starting in the second half of 2017. Intel detailed Hyper-Scaling, a marketing term for a suite of techniques used to scale a transistor, SAQP, a single dummy gate and contact over active gate (COAG).
Samsung
Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 mm contacted gate pitch, 51 nm metal pitch, dual-depth shallow trench isolation (STI), and had single dummy gate.
Samsung 128 Mib SRAM demo 10 nm wafer | |||||||||||||||
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10 nm Microprocessors
- MediaTek
- Qualcomm
- Xiaomi
This list is incomplete; you can help by expanding it.
10 nm Microarchitectures
- Intel
- Qualcomm
This list is incomplete; you can help by expanding it.
Documents
- Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling
- Intel Technoogy & Manufacturing Day presentation, 10 nm
- Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law
References
- Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
- Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
- Seo, K-I., et al. "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
- Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
- Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
- Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
- Samsung's actual transitor size was measured by ChipWorks/TechInsight based on the Qualcomm Snapdragon 835 which is manufactured on Samsung's 10nm process.