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Difference between revisions of "350 nm lithography process"
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|Process Name | |Process Name | ||
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| | | | ||
+ | |Gate Oxide | ||
|Contacted Gate Pitch | |Contacted Gate Pitch | ||
|Interconnect Pitch (M1P) | |Interconnect Pitch (M1P) | ||
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| colspan="2" | 3.3 V || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | | | colspan="2" | 3.3 V || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | | + | | colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | || colspan="2" | |
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! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ | ! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ | ||
+ | |- | ||
+ | | || || || || || || || || 6.5 nm || || || || || || || || || || || || || | ||
|- | |- | ||
| 550 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | | 550 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | ||
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== References == | == References == | ||
* Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998. | * Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998. | ||
+ | * von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722. |
Revision as of 18:15, 29 May 2017
The 350 nanometer lithography process (350 nm or 0.35 µm) is a full node semiconductor manufacturing process following the 500 nm process node. Commercial integrated circuit manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by 250 nm in 1999.
Contents
Industry
Fab |
---|
Process Name |
1st Production |
Voltage |
Metal Layers |
|
Gate Oxide |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell |
Intel | IBM | AMD | AMD | DEC | Fujitsu | IDT | NEC | TI | Motorola | Hitachi | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P854 | CS-34 | CS-34EX | CMOS-6 | CS-60 | HiPerMOS 2 | ||||||||||||||||
1994 | 1994 | 1995 | 1995 | 1996 | 1996 | 1995 | 1997 | 1996 | |||||||||||||
3.3 V | |||||||||||||||||||||
4 | 5 | 5 | 5 | 4 | 5 | 3 | 4 | 5 | |||||||||||||
Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ | Value | 500 nm Δ |
6.5 nm | |||||||||||||||||||||
550 nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
880 nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
18.1 µm² | 0.41x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | 21.67 µm² | ?x | ? µm² | ?x |
Design Rules
Intel 0.350 micron Design Rules | ||
---|---|---|
Layer | Pitch | Thick |
Isolation | ? nm | ? nm |
Polysilicon | ? nm | ? nm |
Metal 1 | 880 nm | 600 nm |
Metal 2 | 1.16 µm | 800 nm |
Metal 3 | 1.16 µm | 800 nm |
Metal 4 | 1.70 µm | 1.70 µm |
350 nm Microprocessors
- Intel
- AMD
- DEC
- HAL
- Fujitsu
- IBM
- Cyrix
- MIPS
- Sun
- NEC
- Parallax
This list is incomplete; you can help by expanding it.
350 nm Microcontrollers
This list is incomplete; you can help by expanding it.
350 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
- von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722.