Semiconductor & Computer Engineering
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Difference between revisions of "10 nm lithography process"
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| ? nm || ?x || 48 nm<ref name="samsung">Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.</ref> || 0.75x || ? nm || ?x || ? nm || ?x | | ? nm || ?x || 48 nm<ref name="samsung">Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.</ref> || 0.75x || ? nm || ?x || ? nm || ?x | ||
|- | |- | ||
| − | | ? µm² || ?x || 0.049 µm²<ref name="samsung2"> | + | | ? µm² || ?x || 0.049 µm²<ref name="samsung2">Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).</ref> || 0.61x || ? µm² || ?x || ? nm || ?x |
|- | |- | ||
| ? µm² || ?x || 0.040 µm²<ref name="samsung2" /> || 0.63x || ? µm² || ?x || ? nm || ?x | | ? µm² || ?x || 0.040 µm²<ref name="samsung2" /> || 0.63x || ? µm² || ?x || ? nm || ?x | ||
{{scrolling table/end}} | {{scrolling table/end}} | ||
| + | |||
| + | === Samsung === | ||
| + | Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. | ||
| + | |||
| + | {| class="collapsible collapsed wikitable" | ||
| + | |- | ||
| + | ! colspan="2" | Samsung 128 Mib SRAM demo 10 nm wafer<ref name="samsung2" /> | ||
| + | |- | ||
| + | | | ||
| + | <table class="wikitable"> | ||
| + | <tr><th>Technology</th><td>10nm FinFET</td></tr> | ||
| + | <tr><th>Supply voltage</th><td>1.8 V (i/o)</td></tr> | ||
| + | <tr><th>Bit cell size</th><td>0.040 µm²</td></tr> | ||
| + | <tr><th>macro configs</th><td>256x512 Kib</td></tr> | ||
| + | <tr><th>Capacity</th><td>256 Mib</td></tr> | ||
| + | <tr><th>Test Features</th><td>Programmable E-fuse</td></tr> | ||
| + | <tr><th>Die Size</th><td>75.6mm2²</td></tr> | ||
| + | </table> | ||
| + | | [[File:samsung 10nm SRAM block.png|400px]] | ||
| + | |} | ||
== 10 nm Microprocessors== | == 10 nm Microprocessors== | ||
Revision as of 19:00, 10 March 2017
Semiconductor lithography processes technology
The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun in late 2016. This technology is set to be replaced by 7 nm process 2019.
Industry
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Fab |
|---|
| Process Name |
| 1st Production |
| |
| Fin Pitch |
| Fin Width |
| Fin Height |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HP) |
| SRAM bit cell (HD) |
| Intel | Samsung | TSMC | SK Hynix | ||||
|---|---|---|---|---|---|---|---|
| P1274 | 10LPE 1st generation; 10 nm Low Power Early , 10LPP2nd generation; 10 nm Low Power Performance , 10LPU3rd generation; 10 nm Low Power Ultimate |
||||||
| 2017 | 2017 | 2017 | 2017 | ||||
| Value | 14 nm Δ | Value | 14 nm Δ | Value | 16 nm Δ | Value | 18 nm Δ |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| 54 nm[1] | 0.77x | 64 nm[2] | 0.82x | ? nm | ?x | ? nm | ?x |
| ? nm | ?x | 48 nm[2] | 0.75x | ? nm | ?x | ? nm | ?x |
| ? µm² | ?x | 0.049 µm²[3] | 0.61x | ? µm² | ?x | ? nm | ?x |
| ? µm² | ?x | 0.040 µm²[3] | 0.63x | ? µm² | ?x | ? nm | ?x |
Samsung
Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process.
| Samsung 128 Mib SRAM demo 10 nm wafer[3] | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||||||||
10 nm Microprocessors
- MediaTek
- Qualcomm
- Xiaomi
This list is incomplete; you can help by expanding it.
10 nm Microarchitectures
- Intel
- Qualcomm
This list is incomplete; you can help by expanding it.
References
- ↑ Based on a presentation by Mark Bohr, Intel
- ↑ 2.0 2.1 Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
- ↑ 3.0 3.1 3.2 Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).