From WikiChip
Difference between revisions of "10 nm lithography process"
(→10 nm Microprocessors) |
(→Industry: +samsung info) |
||
Line 33: | Line 33: | ||
| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | | ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | ||
|- | |- | ||
− | | 54 nm<ref>Based on a presentation by Mark Bohr, Intel</ref> || 0.77x || | + | | 54 nm<ref>Based on a presentation by Mark Bohr, Intel</ref> || 0.77x || 64 nm<ref name="samsung" /> || 0.82x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
− | | ? nm || ?x || | + | | ? nm || ?x || 48 nm<ref name="samsung">Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.</ref> || 0.75x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
− | | ? µm² || ?x || 0.049 µm²<ref>Samsung, [[IEEE]] [[International Solid-State Circuits Conference]] (ISSCC) 2016</ref> || 0.61x || ? µm² || ?x || ? nm || ?x | + | | ? µm² || ?x || 0.049 µm²<ref name="samsung2">Samsung, [[IEEE]] [[International Solid-State Circuits Conference]] (ISSCC) 2016</ref> || 0.61x || ? µm² || ?x || ? nm || ?x |
|- | |- | ||
− | | ? µm² || ?x || 0.040 µm²<ref | + | | ? µm² || ?x || 0.040 µm²<ref name="samsung2" /> || 0.63x || ? µm² || ?x || ? nm || ?x |
{{scrolling table/end}} | {{scrolling table/end}} | ||
Revision as of 16:15, 10 March 2017
The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun in late 2016. This technology is set to be replaced by 7 nm process 2019.
Industry
Fab |
---|
Process Name |
1st Production |
|
Fin Pitch |
Fin Width |
Fin Height |
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell (HP) |
SRAM bit cell (HD) |
Intel | Samsung | TSMC | SK Hynix | ||||
---|---|---|---|---|---|---|---|
P1274 | 10LPE 1st generation; 10 nm Low Power Early , 10LPP2nd generation; 10 nm Low Power Performance , 10LPU3rd generation; 10 nm Low Power Ultimate |
||||||
2017 | 2017 | 2017 | 2017 | ||||
Value | 14 nm Δ | Value | 14 nm Δ | Value | 16 nm Δ | Value | 18 nm Δ |
? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
54 nm[1] | 0.77x | 64 nm[2] | 0.82x | ? nm | ?x | ? nm | ?x |
? nm | ?x | 48 nm[2] | 0.75x | ? nm | ?x | ? nm | ?x |
? µm² | ?x | 0.049 µm²[3] | 0.61x | ? µm² | ?x | ? nm | ?x |
? µm² | ?x | 0.040 µm²[3] | 0.63x | ? µm² | ?x | ? nm | ?x |
10 nm Microprocessors
- MediaTek
- Qualcomm
- Xiaomi
This list is incomplete; you can help by expanding it.
10 nm Microarchitectures
- Intel
- Qualcomm
This list is incomplete; you can help by expanding it.
References
- ↑ Based on a presentation by Mark Bohr, Intel
- ↑ 2.0 2.1 Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
- ↑ 3.0 3.1 Samsung, IEEE International Solid-State Circuits Conference (ISSCC) 2016