(Updates to Intel 3 production date and Transistor based on 4/11/22 annoucements.) |
(→Specifications) |
||
(13 intermediate revisions by 11 users not shown) | |||
Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
− | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023. | + | The '''3 nanometer ([[3 nm]] or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing |
+ | :process following the [[5 nm lithography process|5 nm process]] node. | ||
+ | Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around [[2023]]. | ||
− | The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | + | The term "[[3 nm]]" is simply a commercial name for a generation of a certain size and its technology, and |
+ | :'''does not''' represent any geometry of the transistor. | ||
== Industry == | == Industry == | ||
+ | ==== [[Intel]] ==== | ||
+ | P1278 Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H [[2024]]/[[2025]] timeframe. | ||
+ | === [[TSMC]] === | ||
+ | N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to | ||
+ | :30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). | ||
+ | If this holds true we could see 300+ MT/mm2. | ||
+ | |||
+ | === [[Samsung]] === | ||
+ | On May 24, [[2017]] Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' | ||
+ | :(''MBCFET''), an extension of a [[Gate-all-around]] (GAA) [[FET]]. | ||
+ | This is planned for somewhere after the [[5 nm]] node but the exact timeline or specification is currently unknown. | ||
+ | |||
+ | == Specifications == | ||
{{future information}} | {{future information}} | ||
− | |||
{{finfet nodes comp | {{finfet nodes comp | ||
<!-- Intel --> | <!-- Intel --> | ||
| process 1 fab = [[Intel]] | | process 1 fab = [[Intel]] | ||
− | | process 1 name = | + | | process 1 name = P1278 (CPU), P1279 (SoC) |
| process 1 date = 2H 2023 | | process 1 date = 2H 2023 | ||
| process 1 lith = EUV | | process 1 lith = EUV | ||
Line 29: | Line 44: | ||
| process 1 gate len = | | process 1 gate len = | ||
| process 1 gate len Δ = | | process 1 gate len Δ = | ||
− | | process 1 cpp = | + | | process 1 cpp = 50 nm |
| process 1 cpp Δ = | | process 1 cpp Δ = | ||
− | | process 1 mmp = | + | | process 1 mmp = 30 nm |
| process 1 mmp Δ = | | process 1 mmp Δ = | ||
| process 1 sram hp = | | process 1 sram hp = | ||
Line 43: | Line 58: | ||
<!-- TSMC --> | <!-- TSMC --> | ||
| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = N3, N3E <info>N3 Enhanced</info> | + | | process 2 name = N3(B), N3E <info>N3 Enhanced</info>, N3P, N3X |
− | | process 2 date = | + | | process 2 date = Q4 2022 |
| process 2 lith = EUV | | process 2 lith = EUV | ||
| process 2 immersion = | | process 2 immersion = | ||
Line 61: | Line 76: | ||
| process 2 gate len = | | process 2 gate len = | ||
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
− | | process 2 cpp = | + | | process 2 cpp = 45 nm (48 nm) |
| process 2 cpp Δ = | | process 2 cpp Δ = | ||
− | | process 2 mmp = | + | | process 2 mmp = 23 nm |
| process 2 mmp Δ = | | process 2 mmp Δ = | ||
− | | process 2 sram hp = | + | | process 2 sram hp = 0.0199 μm<sup>2</sup> |
| process 2 sram hp Δ = | | process 2 sram hp Δ = | ||
− | | process 2 sram hd = | + | | process 2 sram hd = 0.0210 μm<sup>2</sup> |
| process 2 sram hd Δ = | | process 2 sram hd Δ = | ||
| process 2 sram lv = | | process 2 sram lv = | ||
Line 74: | Line 89: | ||
| process 2 dram Δ = | | process 2 dram Δ = | ||
<!-- Samsung --> | <!-- Samsung --> | ||
− | | process | + | | process 3 fab = [[Samsung]] |
− | | process | + | | process 3 name = 3GAE <info>3nm Gate All Around Early</info>, 3GAP <info>3nm Gate All Around Plus</info> |
− | | process | + | | process 3 date = 2H 2022 |
− | | process | + | | process 3 lith = EUV |
− | | process | + | | process 3 immersion = |
− | | process | + | | process 3 exposure = SE |
− | | process | + | | process 3 wafer type = Bulk |
− | | process | + | | process 3 wafer size = 300 mm |
− | | process | + | | process 3 transistor = GAAFET (MBCFET) |
− | | process | + | | process 3 volt = |
− | | process | + | | process 3 delta from = [[5 nm]] Δ |
− | | process | + | | process 3 fin pitch = |
− | | process | + | | process 3 fin pitch Δ = |
− | | process | + | | process 3 fin width = |
− | | process | + | | process 3 fin width Δ = |
− | | process | + | | process 3 fin height = |
− | | process | + | | process 3 fin height Δ = |
− | | process | + | | process 3 gate len = |
− | | process | + | | process 3 gate len Δ = |
− | | process | + | | process 3 cpp = 40 nm |
− | | process | + | | process 3 cpp Δ = |
− | | process | + | | process 3 mmp = 32 nm |
− | | process | + | | process 3 mmp Δ = |
− | | process | + | | process 3 sram hp = |
− | | process | + | | process 3 sram hp Δ = |
− | | process | + | | process 3 sram hd = |
− | | process | + | | process 3 sram hd Δ = |
− | | process | + | | process 3 sram lv = |
− | | process | + | | process 3 sram lv Δ = |
− | | process | + | | process 3 dram = |
− | | process | + | | process 3 dram Δ = <br>. |
}} | }} | ||
− | === Samsung === | + | === 3 nm process nodes === |
− | + | {{see also|Intel 7|Intel 4|Intel 18A}} | |
+ | {| class="wikitable" style="text-align:center" | ||
+ | ! | ||
+ | ! colspan=2 | [[Samsung]] <ref>{{cite book |url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ |title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements |website=WikiChip Fuse |date=5 July 2022}}</ref> | ||
+ | ! colspan=4 | [[TSMC]] <ref>{{cite book |url=https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/ |title=TSMC N3, and Challenges Ahead |date=27 May 2023}}</ref> | ||
+ | ! [[Intel]] <ref>{{cite book |title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A |url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros |date=27 July 2021 |website=AnandTech}}</ref> | ||
+ | |- | ||
+ | ! Process name | ||
+ | | 3GAE (SF3E) | ||
+ | | 3GAP (SF3) | ||
+ | | N3 (N3B) | ||
+ | | N3E | ||
+ | | N3P | ||
+ | | N3X | ||
+ | | [[Intel 3]] | ||
+ | |- | ||
+ | ! Transistor type | ||
+ | | colspan=2 | [[GAAFET]] ([[MBCFET]]) | ||
+ | | colspan=5 | [[FinFET]] | ||
+ | |- | ||
+ | ! Transistor <br>density <br>(MTr/mm<sup>2</sup>) | ||
+ | | 150 | ||
+ | | 190 | ||
+ | | 197 | ||
+ | | 216 | ||
+ | | colspan=2 | 224 | ||
+ | | - | ||
+ | |- | ||
+ | ! Transistor gate <br>pitch (nm) | ||
+ | | 40 | ||
+ | | - | ||
+ | | 45 | ||
+ | | 48 | ||
+ | | - | ||
+ | | - | ||
+ | | 50 | ||
+ | |- | ||
+ | ! Interconnect <br>pitch (nm) | ||
+ | | 32 | ||
+ | | - | ||
+ | | - | ||
+ | | 23 | ||
+ | | - | ||
+ | | - | ||
+ | | 30 | ||
+ | |- | ||
+ | ! SRAM bit-cell <br>size (μm<sup>2</sup>) | ||
+ | | - | ||
+ | | - | ||
+ | | 0.0199 | ||
+ | | 0.021 | ||
+ | | - | ||
+ | | - | ||
+ | | - | ||
+ | |- | ||
+ | ! Release status | ||
+ | | 2022 H1 risk <br>production <br>2022 H2 <br>production <br>2022 shipping | ||
+ | | 2024 Q1 risk <br>production <br>2024 H2 <br>production | ||
+ | | 2022 H1 risk <br>production <br>2022 H2 volume <br>production <br>2023 H1 shipping | ||
+ | | 2023 H2 <br>production | ||
+ | | 2024 H2 <br>production | ||
+ | | 2025 H2 <br>production | ||
+ | | 2024 H1 product <br>manufacturing <br>2024 H2 shipping | ||
+ | |- | ||
+ | |} | ||
== 3 nm Microprocessors== | == 3 nm Microprocessors== | ||
+ | * [[Apple]] | ||
+ | ** [[apple/ax|A17 Pro]] | ||
+ | ** [[apple/ax|A18]] | ||
+ | ** [[apple/ax|A18 Pro]] | ||
+ | ** [[apple/mx|M3]] | ||
+ | ** [[apple/mx|M3 Pro]] | ||
+ | ** [[apple/mx|M3 MAX]] | ||
+ | ** [[apple/mx|M3 Ultra]] | ||
+ | ** [[apple/mx|M4]] | ||
+ | ** [[apple/mx|M4 Pro]] | ||
+ | ** [[apple/mx|M4 Max]] | ||
+ | |||
+ | * [[Qualcomm]] | ||
+ | ** {{qualcomm|Snapdragon 8}} Elite | ||
+ | * [[MediaTek]] | ||
+ | ** {{mediatek|Dimensity}} 9400 | ||
+ | |||
{{expand list}} | {{expand list}} | ||
− | == 3 nm Microarchitectures== | + | == 3 nm Microarchitectures == |
+ | |||
+ | * [[AMD]] | ||
+ | ** {{amd|Zen 5|l=arch}}c | ||
+ | ** {{amd|Zen 6|l=arch}} | ||
+ | |||
+ | === 4 nm Microarchitectures === | ||
+ | * [[AMD]] | ||
+ | ** {{amd|Zen 5|l=arch}} | ||
+ | |||
+ | * [[ARM]] • [[Cortex]] | ||
+ | ** {{armh|Hayes|Cortex-A520|l=arch}} | ||
+ | |||
+ | * [[Neoverse]] V2 | ||
+ | ** [[AWS Graviton4]] | ||
+ | |||
{{expand list}} | {{expand list}} | ||
Latest revision as of 18:56, 19 March 2025
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing
- process following the 5 nm process node.
Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and
- does not represent any geometry of the transistor.
Contents
Industry[edit]
Intel[edit]
P1278 Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H 2024/2025 timeframe.
TSMC[edit]
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to
- 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website).
If this holds true we could see 300+ MT/mm2.
Samsung[edit]
On May 24, 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET
- (MBCFET), an extension of a Gate-all-around (GAA) FET.
This is planned for somewhere after the 5 nm node but the exact timeline or specification is currently unknown.
Specifications[edit]
Process Name | |
---|---|
1st Production | |
Litho- graphy |
Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Tran- sistor |
Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell |
High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell |
eDRAM |
Intel | TSMC | Samsung | |||
---|---|---|---|---|---|
P1278 (CPU), P1279 (SoC) | N3(B), N3E N3 Enhanced , N3P, N3X |
3GAE 3nm Gate All Around Early , 3GAP 3nm Gate All Around Plus
| |||
2H 2023 | Q4 2022 | 2H 2022 | |||
EUV | EUV | EUV | |||
SE | SE | SE | |||
Bulk | Bulk | Bulk | |||
300 mm | 300 mm | 300 mm | |||
FinFET | FinFET | GAAFET (MBCFET) | |||
Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
50 nm | 45 nm (48 nm) | 40 nm | |||
30 nm | 23 nm | 32 nm | |||
0.0199 μm2 | |||||
0.0210 μm2 | |||||
. |
3 nm process nodes[edit]
Samsung [1] | TSMC [2] | Intel [3] | |||||
---|---|---|---|---|---|---|---|
Process name | 3GAE (SF3E) | 3GAP (SF3) | N3 (N3B) | N3E | N3P | N3X | Intel 3 |
Transistor type | GAAFET (MBCFET) | FinFET | |||||
Transistor density (MTr/mm2) |
150 | 190 | 197 | 216 | 224 | - | |
Transistor gate pitch (nm) |
40 | - | 45 | 48 | - | - | 50 |
Interconnect pitch (nm) |
32 | - | - | 23 | - | - | 30 |
SRAM bit-cell size (μm2) |
- | - | 0.0199 | 0.021 | - | - | - |
Release status | 2022 H1 risk production 2022 H2 production 2022 shipping |
2024 Q1 risk production 2024 H2 production |
2022 H1 risk production 2022 H2 volume production 2023 H1 shipping |
2023 H2 production |
2024 H2 production |
2025 H2 production |
2024 H1 product manufacturing 2024 H2 shipping |
3 nm Microprocessors[edit]
- Qualcomm
- Snapdragon 8 Elite
- MediaTek
- Dimensity 9400
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures[edit]
4 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
References[edit]
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017