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Difference between revisions of "5 nm lithography process"

(References)
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The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
 
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
 +
 +
== Overview ==
 +
First introduced by the major foundries around the [[2020]] timeframe, the 5-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack.
  
 
== Industry ==
 
== Industry ==
 +
Only three companies are currently planning or developing a 5-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]].
  
{{future information}}
+
{{node comp|node=5 nm}}
 +
 
 +
=== Intel ===
 +
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in the development phase.
  
{{finfet nodes comp
+
=== TSMC ===
<!-- Intel -->
+
==== N5 ====
| process 1 fab          = [[Intel]]
+
TSMC started its [[risk production]] of the 5-nanometer, '''N5''', node in March 2019 with production expected to start in the first quarter of 2020.
| process 1 name        = P1278 (CPU), P1279 (SoC)
 
| process 1 date        = &nbsp;
 
| process 1 lith        = &nbsp;
 
| process 1 immersion    = &nbsp;
 
| process 1 exposure    = &nbsp;
 
| process 1 wafer type  = Bulk
 
| process 1 wafer size  = 300 mm
 
| process 1 transistor  = &nbsp;
 
| process 1 volt        = &nbsp;
 
| process 1 delta from  = [[7 nm]] Δ
 
| process 1 fin pitch    = &nbsp;
 
| process 1 fin pitch Δ  = &nbsp;
 
| process 1 fin width    = &nbsp;
 
| process 1 fin width Δ  = &nbsp;
 
| process 1 fin height  = &nbsp;
 
| process 1 fin height Δ = &nbsp;
 
| process 1 gate len    = &nbsp;
 
| process 1 gate len Δ  = &nbsp;
 
| process 1 cpp          = &nbsp;
 
| process 1 cpp Δ        = &nbsp;
 
| process 1 mmp          = &nbsp;
 
| process 1 mmp Δ        = &nbsp;
 
| process 1 sram hp      = &nbsp;
 
| process 1 sram hp Δ    = &nbsp;
 
| process 1 sram hd      = &nbsp;
 
| process 1 sram hd Δ    = &nbsp;
 
| process 1 sram lv      = &nbsp;
 
| process 1 sram lv Δ    = &nbsp;
 
| process 1 dram        = &nbsp;
 
| process 1 dram Δ      = &nbsp;
 
<!-- TSMC -->
 
| process 2 fab          = [[TSMC]]
 
| process 2 name        = &nbsp;
 
| process 2 date        = &nbsp;
 
| process 2 lith        = 193 nm
 
| process 2 immersion    = Yes
 
| process 2 exposure    = LELELELE
 
| process 2 wafer type  = Bulk
 
| process 2 wafer size  = 300 mm
 
| process 2 transistor  = FinFET
 
| process 2 volt        = &nbsp;
 
| process 2 delta from  = [[7 nm]] Δ
 
| process 2 fin pitch    = &nbsp;
 
| process 2 fin pitch Δ  = &nbsp;
 
| process 2 fin width    = &nbsp;
 
| process 2 fin width Δ  = &nbsp;
 
| process 2 fin height  = &nbsp;
 
| process 2 fin height Δ = &nbsp;
 
| process 2 gate len    = &nbsp;
 
| process 2 gate len Δ  = &nbsp;
 
| process 2 cpp          = ~44 nm
 
| process 2 cpp Δ        = 0.81x
 
| process 2 mmp          = ~32 nm
 
| process 2 mmp Δ        = 0.84x
 
| process 2 sram hp      = &nbsp;
 
| process 2 sram hp Δ    = &nbsp;
 
| process 2 sram hd      = &nbsp;
 
| process 2 sram hd Δ    = &nbsp;
 
| process 2 sram lv      = &nbsp;
 
| process 2 sram lv Δ    = &nbsp;
 
| process 2 dram        = &nbsp;
 
| process 2 dram Δ      = &nbsp;
 
<!-- GlobalFoundries -->
 
| process 3 fab          = [[GlobalFoundries]]
 
| process 3 name        = &nbsp;
 
| process 3 date        = &nbsp;
 
| process 3 lith        = EUV
 
| process 3 immersion    = &nbsp;
 
| process 3 exposure    = SE
 
| process 3 wafer type  = Bulk
 
| process 3 wafer size  = 300 mm
 
| process 3 transistor  = &nbsp;
 
| process 3 volt        = &nbsp;
 
| process 3 delta from  = [[7 nm]] Δ
 
| process 3 fin pitch    = &nbsp;
 
| process 3 fin pitch Δ  = &nbsp;
 
| process 3 fin width    = &nbsp;
 
| process 3 fin width Δ  = &nbsp;
 
| process 3 fin height  = &nbsp;
 
| process 3 fin height Δ = &nbsp;
 
| process 3 gate len    = &nbsp;
 
| process 3 gate len Δ  = &nbsp;
 
| process 3 cpp          = &nbsp;
 
| process 3 cpp Δ        = &nbsp;
 
| process 3 mmp          = &nbsp;
 
| process 3 mmp Δ        = &nbsp;
 
| process 3 sram hp      = &nbsp;
 
| process 3 sram hp Δ    = &nbsp;
 
| process 3 sram hd      = &nbsp;
 
| process 3 sram hd Δ    = &nbsp;
 
| process 3 sram lv      = &nbsp;
 
| process 3 sram lv Δ    = &nbsp;
 
| process 3 dram        = &nbsp;
 
| process 3 dram Δ      = &nbsp;
 
<!-- Samsung -->
 
| process 4 fab          = [[Samsung]]
 
| process 4 name        = &nbsp;
 
| process 4 date        = &nbsp;
 
| process 4 lith        = EUV
 
| process 4 immersion    = &nbsp;
 
| process 4 exposure    = SE
 
| process 4 wafer type  = Bulk
 
| process 4 wafer size  = 300 mm
 
| process 4 transistor  = FinFET
 
| process 4 volt        = &nbsp;
 
| process 4 delta from  = [[7 nm]] Δ
 
| process 4 fin pitch    = &nbsp;
 
| process 4 fin pitch Δ  = &nbsp;
 
| process 4 fin width    = &nbsp;
 
| process 4 fin width Δ  = &nbsp;
 
| process 4 fin height  = &nbsp;
 
| process 4 fin height Δ = &nbsp;
 
| process 4 gate len    = &nbsp;
 
| process 4 gate len Δ  = &nbsp;
 
| process 4 cpp          = &nbsp;
 
| process 4 cpp Δ        = &nbsp;
 
| process 4 mmp          = &nbsp;
 
| process 4 mmp Δ        = &nbsp;
 
| process 4 sram hp      = &nbsp;
 
| process 4 sram hp Δ    = &nbsp;
 
| process 4 sram hd      = &nbsp;
 
| process 4 sram hd Δ    = &nbsp;
 
| process 4 sram lv      = &nbsp;
 
| process 4 sram lv Δ    = &nbsp;
 
| process 4 dram        = &nbsp;
 
| process 4 dram Δ      = &nbsp;
 
  
<!-- Common Platform -->
+
N5 is planned as a [[full node]] successor to the company's [[N7 node]], featuring 1.8x improvement in logic density. The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, 5 nm makes extensive use of [[EUV]] for more critical layers in order to reduce the [[multi-patterning]] complexity.
| process 5 fab          = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper
 
| process 5 name        = &nbsp;
 
| process 5 date        = &nbsp;
 
| process 5 lith        = EUV
 
| process 5 immersion    = &nbsp;
 
| process 5 exposure    = SE
 
| process 5 wafer type  = Bulk
 
| process 5 wafer size  = 300 mm
 
| process 5 transistor  = GAA
 
| process 5 volt        = &nbsp;
 
| process 5 delta from  = [[7 nm]] Δ
 
| process 5 fin pitch    = -
 
| process 5 fin pitch Δ  = &nbsp;
 
| process 5 fin width    = &nbsp;
 
| process 5 fin width Δ  = &nbsp;
 
| process 5 fin height  = &nbsp;
 
| process 5 fin height Δ = &nbsp;
 
| process 5 gate len    = 12 nm
 
| process 5 gate len Δ  = &nbsp;
 
| process 5 cpp          = 48 nm
 
| process 5 cpp Δ        = 1.00x
 
| process 5 mmp          = &nbsp;
 
| process 5 mmp Δ        = &nbsp;
 
| process 5 sram hp      = &nbsp;
 
| process 5 sram hp Δ    = &nbsp;
 
| process 5 sram hd      = &nbsp;
 
| process 5 sram hd Δ    = &nbsp;
 
| process 5 sram lv      = &nbsp;
 
| process 5 sram lv Δ    = &nbsp;
 
| process 5 dram        = &nbsp;
 
| process 5 dram Δ      = &nbsp;
 
}}
 
  
=== Intel ===
+
{| class="wikitable" style="text-align: center;"
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase.
+
|-
 +
! colspan="3" | N5 PPA vs. [[N7]]
 +
|-
 +
! Speed @ iso-power !! Power @ iso-speed !! Max speed improvement<br>@ Vdd (eLVT)
 +
|-
 +
| ~15% || ~30% || ~25%
 +
|}
  
=== TSMC ===
+
The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. For N5, TSMC is also offering an eLVT library that offers 25% high speed at Vdd. N5 targets both low-power mobile and high-performance compute with this node. In addition to a target density improvement of ~1.8x, TSMC has also improved the analog circuit density by ~1.2x.
The TSMC 5nm node uses a FinFET transistor like their 7nm process, but it makes more extensive use of EUVL. This provides a transistor density improvement of 30%-80%, and a reduction in transistor variability. The process will provide a 15% speed improvement or a 30% reduction in power compared to their standard 7nm process.
 
  
=== Common Platform Alliance Paper ===
+
==== N5P ====
In a joint paper by the [[Common Platform]] (IBM, GlobalFoundries, Samsung) a 5nm node was proposed at the 2017 VLSI Symposium. The paper presents a new horizontally stacked sheet [[gate-all-around]] (GAA) FET with good properties which can be a good candidate for the replacement of FinFET at the 5nm node. The paper reports transistors with an aggressive L<sub>g</sub> of 12 nm and a contacted poly pitch of 48 nm.  
+
As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called '''N5 Performance-enhanced version''' ('''N5P'''). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021.
  
[[File:ibm stacked silicon nanowire transistors.jpg|400px]]
+
=== Samsung ===
 +
==== 5LPE ====
 +
{{empty section}}
 +
==== 4LPE ====
 +
{{empty section}}
  
 
== 5 nm Microprocessors==
 
== 5 nm Microprocessors==
Line 191: Line 49:
 
{{expand list}}
 
{{expand list}}
  
== References ==
+
== Bibliography ==
* TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017
+
* WikiChip Own Research
* Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, 2017 Symposium on VLSI Technology / Circuits
+
* TSMC Technology Symposium, 2017
 +
* TSMC Technology Symposium, 2018
 +
* TSMC Technology Symposium, 2019
 +
* Samsung Foundry Forum, 2019
 +
* Samsung, Arm TechCon, 2019
 +
* TSMC, Arm TechCon, 2019
  
 
[[category:lithography]]
 
[[category:lithography]]

Revision as of 09:41, 13 October 2019

The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 5 nm process is set to begin sometimes around 2020.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Overview

First introduced by the major foundries around the 2020 timeframe, the 5-nanometer process technology is characterized by its use of FinFET transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack.

Industry

Only three companies are currently planning or developing a 5-nanometer node: Intel, TSMC, and Samsung.

 IntelTSMCSamsung
ProcessP1278 (CPU), P1279 (SoC)N5, N5P5LPP
Production2023Q1'20202020
LithoLithographyEUV
Immersion
Exposure
SE (EUV)
DP (193i)
SE (EUV)
DP (193i)
WaferTypeBulk
Size300 mm
xTorTypeFinFETFinFET
Voltage
 Value7 nm ΔValue7 nm ΔValue7 nm Δ
FinPitch27 nm1.0x
Width
Height
Gate Length (Lg)8/10 nm1.0x
Contacted Gate Pitch (CPP)60 nm (HP)
54 nm (HD)
1.0x
1.0x
Minimum Metal Pitch (MMP)36 nm1.0x
SRAMHigh-Perf (HP)0.032 µm²1.0x
High-Density (HD)0.021 µm²0.78x0.026 µm²1.0x
Low-Voltage (LV)

Intel

In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in the development phase.

TSMC

N5

TSMC started its risk production of the 5-nanometer, N5, node in March 2019 with production expected to start in the first quarter of 2020.

N5 is planned as a full node successor to the company's N7 node, featuring 1.8x improvement in logic density. The N5 node continues to use bulk silicon FinFET transistors. Leveraging their experience from 7+, 5 nm makes extensive use of EUV for more critical layers in order to reduce the multi-patterning complexity.

N5 PPA vs. N7
Speed @ iso-power Power @ iso-speed Max speed improvement
@ Vdd (eLVT)
~15% ~30% ~25%

The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. For N5, TSMC is also offering an eLVT library that offers 25% high speed at Vdd. N5 targets both low-power mobile and high-performance compute with this node. In addition to a target density improvement of ~1.8x, TSMC has also improved the analog circuit density by ~1.2x.

N5P

As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called N5 Performance-enhanced version (N5P). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021.

Samsung

5LPE

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4LPE

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5 nm Microprocessors

This list is incomplete; you can help by expanding it.

5 nm Microarchitectures

This list is incomplete; you can help by expanding it.

Bibliography

  • WikiChip Own Research
  • TSMC Technology Symposium, 2017
  • TSMC Technology Symposium, 2018
  • TSMC Technology Symposium, 2019
  • Samsung Foundry Forum, 2019
  • Samsung, Arm TechCon, 2019
  • TSMC, Arm TechCon, 2019