Semiconductor & Computer Engineering
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Difference between revisions of "45 nm lithography process"
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== Industry == | == Industry == | ||
| − | == | + | {{scrolling table/top|style=text-align: right; | first=Fab |
| − | { | + | |Type |
| + | | | ||
| + | |Contacted Gate Pitch | ||
| + | |Interconnect Pitch (M1P) | ||
| + | |SRAM bit cell (HD) | ||
| + | |SRAM bit cell (LP) | ||
| + | }} | ||
| + | {{scrolling table/mid}} | ||
|- | |- | ||
| − | | || | + | ! colspan="2" | [[Intel]] !! colspan="2" | [[Fujitsu]] !! colspan="2" | [[TI]] !! colspan="2" | [[Toshiba]] / [[Sony]] / [[NEC]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] |
|- | |- | ||
| − | | | + | | colspan="8" | Bulk || colspan="2" | PDSOI |
|- | |- | ||
| − | + | ! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ | |
|- | |- | ||
| − | | | + | | 180 nm || 0.82x || 190 nm || ?x || ? nm || ?x || 180 nm || ?x || 190 nm || 0.76x |
| − | |} | + | |- |
| − | + | | 160 nm || 0.76x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x | |
| − | {| class="wikitable" | + | |- |
| + | | 0.346 µm<sup>2</sup> || 0.61x || 0.225 µm<sup>2</sup> || ?x || 0.255 µm<sup>2</sup> || ?x || 0.248 µm<sup>2</sup> || ?x || 0.370 µm<sup>2</sup> || 0.57x | ||
| + | |- | ||
| + | | || || || || || || || || || | ||
| + | {{scrolling table/end}} | ||
| + | === Design Rules === | ||
| + | {| class="wikitable collapsible collapsed" | ||
|- | |- | ||
! colspan="4" | Design Rules | ! colspan="4" | Design Rules | ||
Revision as of 04:58, 24 April 2016
Semiconductor lithography processes technology
The 45 nm lithography process is a full node semiconductor manufacturing process following the 55 nm process stopgap. Commercial integrated circuit manufacturing using 45 nm process began in 2007. This technology was superseded by the 40 nm process (HN) / 32 nm process (FN) in 2010.
Contents
Industry
| Fab |
|---|
| Type |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell (HD) |
| SRAM bit cell (LP) |
| Intel | Fujitsu | TI | Toshiba / Sony / NEC | IBM / Toshiba / Sony / AMD | |||||
|---|---|---|---|---|---|---|---|---|---|
| Bulk | PDSOI | ||||||||
| Value | 65 nm Δ | Value | 65 nm Δ | Value | 65 nm Δ | Value | 65 nm Δ | Value | 65 nm Δ |
| 180 nm | 0.82x | 190 nm | ?x | ? nm | ?x | 180 nm | ?x | 190 nm | 0.76x |
| 160 nm | 0.76x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| 0.346 µm2 | 0.61x | 0.225 µm2 | ?x | 0.255 µm2 | ?x | 0.248 µm2 | ?x | 0.370 µm2 | 0.57x |
Design Rules
| Design Rules | |||
|---|---|---|---|
| Layer | Pitch | Thick | Aspect Ratio |
| Isolation | 200 nm | 200 nm | - |
| Contacted Gate | 180 nm | 60 nm | -- |
| Metal 1 | 160 nm | 144 nm | 1.8 |
| Metal 2 | 160 nm | 144 nm | 1.8 |
| Metal 3 | 160 nm | 144 nm | 1.8 |
| Metal 4 | 240 nm | 216 nm | 1.8 |
| Metal 5 | 280 nm | 252 nm | 1.8 |
| Metal 6 | 360 nm | 324 nm | 1.8 |
| Metal 7 | 560 nm | 504 nm | 1.7 |
| Metal 8 | 810 nm | 720 nm | 1.8 |
| Metal 9 | 30.5 µm | 7 µm | 0.4 |
TSMC
| Measurement | |
| Contacted Gate Pitch | 162 nm |
| Interconnect Pitch (M1P) | ? nm |
| SRAM bit cell | 0.242 µm2 |
Crolles2 Alliance
| Measurement | |
| Contacted Gate Pitch | 140 nm |
| Interconnect Pitch (M1P) | ? nm |
| SRAM bit cell | 0.250 µm2 |
45 nm Microprocessors
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45 nm System on Chips
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45 nm Microarchitectures
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