From WikiChip
2 µm lithography process
Revision as of 22:57, 27 June 2017 by David (talk | contribs) (Industry)

The 2 µm lithography process was the semiconductor process technology used by the some semiconductor companies in the mid to late 1980s. By the mid 80s this process was replaced by 1.5 µm, 1.3 µm, and 1.2 µm processes.

Industry

Foundry
Process Name
1st Production
WaferType
Size
TransistorTechnology
Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcellHigh-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcelleDRAM
IntelIntelIntelAMDMotorolaSTMicroToshibaTIHitachi
CHMOS IIP414.1 (HMOS-II)P421.X (HMOS-E)     Hi-CMOS II
19791980198019921982
BulkBulkBulkBulkBulkBulkBulkBulk
         
CMOSpMOS
PlanarPlanarPlanar
5 V5 V5 V5 V
1
Value3 µm ΔValueValueN/AValueN/AValueN/AValueN/AValueN/AValueN/AValue3 µm
2 µm0.80x2 µm0.67x
5.6 µm           
8 µm         3 µm1.00x
            
1740 µm²         303.8 µm²0.34x
            
            

Microprocessors

This list is incomplete; you can help by expanding it.

References

  • Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
  • Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.