The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 5 nm process is set to begin sometimes around 2020.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Overview

First introduced by the major foundries around the 2020 timeframe, the 5-nanometer process technology is characterized by its use of FinFET transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack.

Industry

Only three companies are currently planning or developing a 5-nanometer node: Intel, TSMC, and Samsung.

		Intel		TSMC		Samsung
Process		P1278 (CPU), P1279 (SoC)		N5, N5P		5LPP
Production		2023		Q1'2020		2020
Litho	Lithography	EUV
	Immersion Exposure			SE (EUV) DP (193i)		SE (EUV) DP (193i)
Wafer	Type	Bulk
	Size	300 mm
xTor	Type			FinFET		FinFET
	Voltage
		Value	7 nm Δ	Value	7 nm Δ	Value	7 nm Δ
Fin	Pitch					27 nm	1.0x
	Width
	Height
Gate Length (Lg)						8/10 nm	1.0x
Contacted Gate Pitch (CPP)						60 nm (HP) 54 nm (HD)	1.0x 1.0x
Minimum Metal Pitch (MMP)						36 nm	1.0x
SRAM	High-Perf (HP)					0.032 µm²	1.0x
	High-Density (HD)			0.021 µm²	0.78x	0.026 µm²	1.0x
	Low-Voltage (LV)

Intel

In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in the development phase.

TSMC

N5

TSMC started its risk production of the 5-nanometer, N5, node in March 2019 with production expected to start in the first quarter of 2020.

N5 is planned as a full node successor to the company's N7 node, featuring 1.8x improvement in logic density. The N5 node continues to use bulk silicon FinFET transistors. Leveraging their experience from 7+, 5 nm makes extensive use of EUV for more critical layers in order to reduce the multi-patterning complexity.

N5 PPA vs. N7
Speed @ iso-power	Power @ iso-speed	Max speed improvement @ Vdd (eLVT)
~15%	~30%	~25%

The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. For N5, TSMC is also offering an eLVT library that offers 25% high speed at Vdd. N5 targets both low-power mobile and high-performance compute with this node. In addition to a target density improvement of ~1.8x, TSMC has also improved the analog circuit density by ~1.2x.

N5P

As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called N5 Performance-enhanced version (N5P). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021.

Samsung

5LPE

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4LPE

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5 nm Microprocessors

• PEZY
  • PEZY-SC4

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5 nm Microarchitectures

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Bibliography

• WikiChip Own Research
• TSMC Technology Symposium, 2017
• TSMC Technology Symposium, 2018
• TSMC Technology Symposium, 2019
• Samsung Foundry Forum, 2019
• Samsung, Arm TechCon, 2019
• TSMC, Arm TechCon, 2019