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Difference between revisions of "28 nm lithography process"

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== Industry ==
 
== Industry ==
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
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|Process Name
 
  |Transistor
 
  |Transistor
 
  |Wafer
 
  |Wafer
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|-
 
|-
 
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]]
 
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]]
 +
|- style="text-align: center;"
 +
| colspan="2" | 28LP || colspan="2" |   || colspan="2" | 28SLP || colspan="2" |   || colspan="2" |  
 
|- style="text-align: center;"
 
|- style="text-align: center;"
 
| colspan="10" | Planar
 
| colspan="10" | Planar
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! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ
 
! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ
 
|-
 
|-
−
| 90 nm || 0.70x || 117 nm || 0.72x || ?nm || ?x || ?nm || ?x || ?nm || ?x
+
| 114 nm || 0.88x || 117 nm || 0.72x || 114 nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
−
| 96 nm || 0.82x || 95 nm || 0.81x || ?nm || ?x || ?nm || ?x || ?nm || ?x
+
| 114 nm || 0.97x || 95 nm || 0.81x || 114 nm || ?x || ?nm || ?x || ?nm || ?x
 
|-
 
|-
 
| 0.120 µm² || ?x || 0.127 µm² || 0.52x || 0.120 µm² || ?x || 0.120 µm² || ?x || 0.124 µm² || ?x
 
| 0.120 µm² || ?x || 0.127 µm² || 0.52x || 0.120 µm² || ?x || 0.120 µm² || ?x || 0.124 µm² || ?x
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{{expand list}}
 
{{expand list}}
 +
 +
== References ==
 +
* Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
 +
* James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.

Revision as of 17:49, 28 March 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.

Industry

Fab
Process Name​
Transistor​
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (LP)​
SRAM bit cell (HC)
Samsung TSMC GlobalFoundries STMicroelectronics UMC
28LP   28SLP    
Planar
300 mm
Value 40 nm Δ Value 40 nm Δ Value 40 nm Δ Value 40 nm Δ Value 40 nm Δ
114 nm 0.88x 117 nm 0.72x 114 nm  ?x  ?nm  ?x  ?nm  ?x
114 nm 0.97x 95 nm 0.81x 114 nm  ?x  ?nm  ?x  ?nm  ?x
0.120 µm²  ?x 0.127 µm² 0.52x 0.120 µm²  ?x 0.120 µm²  ?x 0.124 µm²  ?x
0.155 µm² 0.197 µm²  ?x  ? µm²  ?x
0.152 µm²  ?x

28 nm Microprocessors

This list is incomplete; you can help by expanding it.

28 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  • Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  • James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
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