Semiconductor & Computer Engineering
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Difference between revisions of "32 nm lithography process"
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| colspan="2" | PDSOI || colspan="10" | Bulk | | colspan="2" | PDSOI || colspan="10" | Bulk | ||
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| − | ! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ !! Value !! [[ | + | ! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ !! Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[45 nm]] Δ |
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| − | | 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 113.4 nm || | + | | 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 113.4 nm || 0.88x || 120 nm || 0.71x || 126 nm || 0.66x |
|- | |- | ||
| − | | ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 113.4 nm || | + | | ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 113.4 nm || 0.97x || ? nm || ?x || ?nm || ?x |
|- | |- | ||
| − | | 0.15 µm<sup>2</sup> || 0.41 || 0.171 µm<sup>2</sup> || 0.63x || 0.15 µm<sup>2</sup> || 0.62x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || | + | | 0.15 µm<sup>2</sup> || 0.41 || 0.171 µm<sup>2</sup> || 0.63x || 0.15 µm<sup>2</sup> || 0.62x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || 0.64x || 0.157 µm<sup>2</sup> || 0.42x |
{{scrolling table/end}} | {{scrolling table/end}} | ||
=== Design Rules === | === Design Rules === | ||
Revision as of 04:10, 24 April 2016
Semiconductor lithography processes technology
The 32 nm lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.
Contents
Industry
TSMC cancelled its planned 32nm node process.
| Fab |
|---|
| Type |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |
| Common Platform | Intel | TSMC | Samsung | Toshiba / NEC | Common Platform 2 | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| PDSOI | Bulk | ||||||||||
| Value | 45 nm Δ | Value | 45 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 45 nm Δ |
| 130 nm | 0.68x | 112.5 nm | 0.63x | 130 nm | 0.80x | 113.4 nm | 0.88x | 120 nm | 0.71x | 126 nm | 0.66x |
| ? nm | ?x | 112.5 nm | 0.70x | ? nm | ?x | 113.4 nm | 0.97x | ? nm | ?x | ?nm | ?x |
| 0.15 µm2 | 0.41 | 0.171 µm2 | 0.63x | 0.15 µm2 | 0.62x | 0.120 µm2 | ?x | 0.124 µm2 | 0.64x | 0.157 µm2 | 0.42x |
Design Rules
| Intel 32nm Design Rules | |||
|---|---|---|---|
| Layer | Pitch | Thick | Aspect Ratio |
| Isolation | 140 nm | 200 | - |
| Contacted Gate | 112.5 nm | 35 nm | -- |
| Metal 1 | 112.5 nm | 95 nm | 1.7 |
| Metal 2 | 112.5 nm | 95 nm | 1.7 |
| Metal 3 | 112.5 nm | 95 nm | 1.7 |
| Metal 4 | 168.8 nm | 151 nm | 1.8 |
| Metal 5 | 225.0 nm | 204 nm | 1.8 |
| Metal 6 | 337.6 nm | 303 nm | 1.8 |
| Metal 7 | 450.1 nm | 388 nm | 1.7 |
| Metal 8 | 566.5 nm | 504 nm | 1.8 |
| Metal 9 | 19.4 µm | 8 µm | 1.5 |
32 nm Microprocessors
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32 nm System on Chips
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32 nm Microarchitectures
- Intel:
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