Semiconductor & Computer Engineering
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Difference between revisions of "28 nm lithography process"
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| [[SRAM]] bit cell || 0.120 µm<sup>2</sup> || ?x | | [[SRAM]] bit cell || 0.120 µm<sup>2</sup> || ?x | ||
| + | |} | ||
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| + | === TSMC === | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | || Measurement || Notes | ||
| + | |- | ||
| + | | Contacted Gate Pitch || 117 nm || | ||
| + | |- | ||
| + | | Interconnect Pitch (M1P) || ? nm || | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || 0.127 µm<sup>2</sup> || High Density | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || 0.155 µm<sup>2</sup> || Low Voltage | ||
|} | |} | ||
Revision as of 23:02, 23 April 2016
Semiconductor lithography processes technology
The 28 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.
Industry
Samsung
| Measurement | Scaling from 40 nm | |
| Contacted Gate Pitch | 90 nm | 0.70x |
| Interconnect Pitch (M1P) | 96 nm | 0.82x |
| SRAM bit cell | 0.120 µm2 | ?x |
TSMC
| Measurement | Notes | |
| Contacted Gate Pitch | 117 nm | |
| Interconnect Pitch (M1P) | ? nm | |
| SRAM bit cell | 0.127 µm2 | High Density |
| SRAM bit cell | 0.155 µm2 | Low Voltage |
28 nm Microprocessors
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28 nm System on Chips
- Intel
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