Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "10 nm lithography process"
m |
|||
| Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
The '''10 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[14 nm lithography process|14 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 10 nm process is set to begin in 2017. This technology is set to be replaced by [[7 nm lithography process|7 nm process]] 2019. | The '''10 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[14 nm lithography process|14 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 10 nm process is set to begin in 2017. This technology is set to be replaced by [[7 nm lithography process|7 nm process]] 2019. | ||
| + | == Industry == | ||
| + | |||
| + | === Intel === | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | || Measurement || Scaling from [[14 nm]] | ||
| + | |- | ||
| + | | Fin Pitch || ? nm || ?x | ||
| + | |- | ||
| + | | Contacted Gate Pitch || 55 nm || 0.78x | ||
| + | |- | ||
| + | | Interconnect Pitch (M1P) || 38 nm || 0.74x | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x | ||
| + | |} | ||
| + | |||
| + | === Global Foundries / Samsung === | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | || Measurement || Scaling from [[14 nm]] || Notes | ||
| + | |- | ||
| + | | Fin Pitch || ? nm || ?x || | ||
| + | |- | ||
| + | | Contacted Gate Pitch || 64 nm || 0.82x || | ||
| + | |- | ||
| + | | Interconnect Pitch (M1P) || 48 nm || 0.75x || | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || 0.049 µm<sup>2</sup> || 0.61x || High Performance | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || 0.04 µm<sup>2</sup> || 0.63x || High Density | ||
| + | |} | ||
| + | |||
| + | === TSMC === | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | || Measurement || Scaling from [[16 nm]] | ||
| + | |- | ||
| + | | Fin Pitch || ? nm || ?x | ||
| + | |- | ||
| + | | Contacted Gate Pitch || 70 nm || 0.78x | ||
| + | |- | ||
| + | | Interconnect Pitch (M1P) || 46 nm || 0.72x | ||
| + | |- | ||
| + | | [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x | ||
| + | |} | ||
== 10 nm Microprocessors== | == 10 nm Microprocessors== | ||
Revision as of 21:14, 23 April 2016
Semiconductor lithography processes technology
The 10 nm lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. Commercial integrated circuit manufacturing using 10 nm process is set to begin in 2017. This technology is set to be replaced by 7 nm process 2019.
Contents
Industry
Intel
| Measurement | Scaling from 14 nm | |
| Fin Pitch | ? nm | ?x |
| Contacted Gate Pitch | 55 nm | 0.78x |
| Interconnect Pitch (M1P) | 38 nm | 0.74x |
| SRAM bit cell | ? µm2 | ?x |
Global Foundries / Samsung
| Measurement | Scaling from 14 nm | Notes | |
| Fin Pitch | ? nm | ?x | |
| Contacted Gate Pitch | 64 nm | 0.82x | |
| Interconnect Pitch (M1P) | 48 nm | 0.75x | |
| SRAM bit cell | 0.049 µm2 | 0.61x | High Performance |
| SRAM bit cell | 0.04 µm2 | 0.63x | High Density |
TSMC
| Measurement | Scaling from 16 nm | |
| Fin Pitch | ? nm | ?x |
| Contacted Gate Pitch | 70 nm | 0.78x |
| Interconnect Pitch (M1P) | 46 nm | 0.72x |
| SRAM bit cell | ? µm2 | ?x |
10 nm Microprocessors
This list is incomplete; you can help by expanding it.
10 nm System on Chips
This list is incomplete; you can help by expanding it.
10 nm Microarchitectures
This list is incomplete; you can help by expanding it.