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Difference between revisions of "16 nm lithography process"

(TSMC)
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| colspan="2" | 300mm
 
| colspan="2" | 300mm
 
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! Value<ref>TechInsights/Chipworks, Kevin Gibb, The ConFab 2016</ref> !! [[20 nm]] Δ  
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! Value !! [[20 nm]] Δ  
 
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| 48 nm || rowspan="3" | N/A
 
| 48 nm || rowspan="3" | N/A
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| 90 nm || 1.03x
 
| 90 nm || 1.03x
 
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| 70 nm || 1.09x
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| 64 nm || 0.96x
 
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| 0.07 µm²<ref name="tsmc">Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.</ref> || 0.86x
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| 0.07 µm² || 0.86x
 
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{| class="collapsible collapsed wikitable"
 
{| class="collapsible collapsed wikitable"
 
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! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer<ref name="tsmc" />
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! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer
 
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== References ==
 
== References ==
{{reflist}}
+
* Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
 +
* Wu, Shien-Yang, et al. "A 16nm FinFET CMOS technology for mobile SoC and computing applications." Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013.
 +
* TechInsights/Chipworks, Kevin Gibb, The ConFab 2016
  
  
 
[[Category:Lithography]]
 
[[Category:Lithography]]

Revision as of 18:14, 15 March 2017

The 16 nanometer (16 nm) lithography process is a full node semiconductor manufacturing process following the 20 nm process stopgap. Commercial integrated circuit manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with 10 nm process in 2017.

Industry

Fab
Wafer​
 ​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
TSMC
300mm
Value 20 nm Δ
48 nm N/A
 ? nm
37 nm
90 nm 1.03x
64 nm 0.96x
0.07 µm² 0.86x

TSMC

TSMC demonstrated their 128 Mebibit SRAM wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC.

16 nm Microprocessors

This list is incomplete; you can help by expanding it.

16 nm Microarchitectures

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References

  • Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
  • Wu, Shien-Yang, et al. "A 16nm FinFET CMOS technology for mobile SoC and computing applications." Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013.
  • TechInsights/Chipworks, Kevin Gibb, The ConFab 2016