Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "250 nm lithography process"
(→Industry) |
|||
| (2 intermediate revisions by 2 users not shown) | |||
| Line 3: | Line 3: | ||
== Industry == | == Industry == | ||
| − | The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] | + | The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electrode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels. |
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
| Line 28: | Line 28: | ||
! Value !! [[350 nm]] Δ !! Value !! 250 nm Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ | ! Value !! [[350 nm]] Δ !! Value !! 250 nm Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ | ||
|- | |- | ||
| − | | 500 nm || 0.91x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || | + | | 500 nm || 0.91x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || 640 nm || 0.8x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
| − | | 640 nm || 0.72x || ? nm || ?x || 700 nm || ?x || 880 nm || ?x || 850 nm || ?x || 840 nm || ?x || 940 nm || ?x || 900 nm || ?x || | + | | 640 nm || 0.72x || ? nm || ?x || 700 nm || ?x || 880 nm || ?x || 850 nm || ?x || 840 nm || ?x || 940 nm || ?x || 900 nm || ?x || 640 nm || 0.67x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
|- | |- | ||
| 10.26 µm² || 0.57x || 9.26 µm² || 0.90x || 8.6 µm² || ?x || ? µm² || ?x || 10.5 µm² || ?x || 11.5 µm² || ?x || 11.2 µm² || ?x || ? µm² || ?x || 7.56 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || 12.77 µm² || ?x | | 10.26 µm² || 0.57x || 9.26 µm² || 0.90x || 8.6 µm² || ?x || ? µm² || ?x || 10.5 µm² || ?x || 11.5 µm² || ?x || 11.2 µm² || ?x || ? µm² || ?x || 7.56 µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || 12.77 µm² || ?x | ||
| Line 131: | Line 131: | ||
* Seshan, Krishna, Timothy J. Maloney, and Kenneth J. Wu. "The quality and reliability of Intel's quarter micron process." (1998). | * Seshan, Krishna, Timothy J. Maloney, and Kenneth J. Wu. "The quality and reliability of Intel's quarter micron process." (1998). | ||
* Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998. | * Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998. | ||
| + | |||
| + | [[category:lithography]] | ||
Latest revision as of 15:18, 21 August 2022
Semiconductor lithography processes technology
The 250 nanometer (250 nm) lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.
Contents
Industry[edit]
The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm wafers, SiO2 dielectric and polysilicon electrode. It used Al inter-connects and an Si channels.
| Fab |
|---|
| Process Name |
| 1st Production |
| Wafer |
| Metal Layers |
| |
| Contacted Gate Pitch |
| Interconnect Pitch (M1P) |
| SRAM bit cell |
| Intel | IBM | AMD | TI | DEC | IDT | Fujitsu | TSMC | Samsung | Toshiba | Motorola | NEC | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| P856 | P856.5 | CMOS-6X | CS-44/CS44E/CS44E-Mod | C07 | CMOS-7 | CMOS-10+ | CS-70 | HiPerMOS 4 | |||||||||||||||||
| 1997 | 1998 | 1997 | 1998 | 1999 | ? | ? | ? | ? | 1998 | 1998 | 1997 | ||||||||||||||
| 200 mm | |||||||||||||||||||||||||
| 5 | 5 | 5 | 5 | 4 | |||||||||||||||||||||
| Value | 350 nm Δ | Value | 250 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ | Value | 350 nm Δ |
| 500 nm | 0.91x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x | 640 nm | 0.8x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| 640 nm | 0.72x | ? nm | ?x | 700 nm | ?x | 880 nm | ?x | 850 nm | ?x | 840 nm | ?x | 940 nm | ?x | 900 nm | ?x | 640 nm | 0.67x | ? nm | ?x | ? nm | ?x | ? nm | ?x | ? nm | ?x |
| 10.26 µm² | 0.57x | 9.26 µm² | 0.90x | 8.6 µm² | ?x | ? µm² | ?x | 10.5 µm² | ?x | 11.5 µm² | ?x | 11.2 µm² | ?x | ? µm² | ?x | 7.56 µm² | ?x | ? µm² | ?x | ? µm² | ?x | ? µm² | ?x | 12.77 µm² | ?x |
Design Rules[edit]
| Intel 0.25 micron Design Rules (P856) | |||
|---|---|---|---|
| Layer | Pitch | Thick | Aspect Ratio |
| Isolation | ? nm | ? nm | - |
| Polysilicon | ? nm | ? nm | - |
| Metal 1 | 640 nm | 480 nm | 1.6 |
| Metal 2 | 930 nm | 900 nm | 2.0 |
| Metal 3 | 930 nm | 900 nm | 2.0 |
| Metal 4 | 1.60 µm | 1.325 µm | 1.7 |
| Metal 5 | 2.56 µm | 1.900 nm | 1.6 |
| Intel 0.25 %5 shrink micron Design Rules (P856.5) | |||
|---|---|---|---|
| Layer | Pitch | Thick | Aspect Ratio |
| Isolation | ? nm | ? nm | - |
| Polysilicon | ? nm | ? nm | - |
| Metal 1 | 608 nm | 480 nm | 1.6 |
| Metal 2 | 882 nm | 900 nm | 2.0 |
| Metal 3 | 882 nm | 900 nm | 2.0 |
| Metal 4 | 1.520 µm | 1.325 µm | 1.7 |
| Metal 5 | 2.432 µm | 1.900 nm | 1.6 |
250 nm Microprocessors[edit]
- AMD
- Centaur
- Cyrix
- DEC
- IBM
- Intel
- Pentium MMX, 200-300 MHz September, 1997
- Pentium II, 333-450 MHz, January 1998
- Mobile Pentium II, 233-300 MHz, April 1998
- Pentium II Xeon
- Celeron, 200-300 MHz, April 1998
- Celeron, 300-533 MHz, August 1998
- Celeron Notebook, 266-466 MHz, January 1999
- Pentium III, 450-600 MHz, February 1999
- Pentium III Xeon
- MIPS
- R10000, 1997, fab'ed by NEC
- Qualcomm
- Sun
This list is incomplete; you can help by expanding it.
250 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
References[edit]
- Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
- Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
- Seshan, Krishna, Timothy J. Maloney, and Kenneth J. Wu. "The quality and reliability of Intel's quarter micron process." (1998).
- Thompson, Scott. "MOS scaling: Transistor challenges for the 21st century." Intel Technology Journal. 1998.