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| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
| ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
−
| 44 µm<sup>2</sup> || 0.40x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
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| 44 µm² || 0.40x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x
 
{{scrolling table/end}}
 
{{scrolling table/end}}
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=== DEC ===
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{{see also|dec/process|l1=DEC's Process Technology History}}
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DEC's half-micron process, '''CMOS-5''', which was used for their microprocessors such as the {{decc|Alpha 21164|l=arch}} used a Cabalt di-silicide in diffusion and poly with a channel length of 0.365 µm with a T<sub>OX</sub> of 9 nm along with 4 metal layers of AlCu (Aluminum Copper). The process had a Vtn/p = 0.5/-0.5 V and a supply voltage of 3.3 V.
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{| class="wikitable collapsible collapsed"
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|-
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! colspan="3" | DEC's Design Rules
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|-
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! Layer !! Pitch !! Thickness
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|-
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| M1 || 1.50 µm || 0.84 µm
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|-
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| M2 || 1.75 µm || 0.84 µm
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|-
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| M3 || 5.00 µm || 1.53 µm
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|-
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| M4 || 6.00 µm || 1.53 µm
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|}
  
 
== 500 nm Microprocessors ==
 
== 500 nm Microprocessors ==
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* NexGen
 
* NexGen
 
** {{nexgen|Nx586}}
 
** {{nexgen|Nx586}}
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* Qualcomm
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** {{qualcomm|MSM2}}
 
* Ross
 
* Ross
 
** {{ross|hyperSPARC}} ("Colorado 2")
 
** {{ross|hyperSPARC}} ("Colorado 2")
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== 500 nm Microarchitectures ==
 
== 500 nm Microarchitectures ==
 
* AMD
 
* AMD
−
** {{amd|microarchitectures/k5|K5}}
+
** {{amd|K5|l=arch}}
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* DEC
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** {{decc|Alpha 21164|l=arch}}
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* Intel
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** {{intel|80186|l=arch}} (embedded [[IP cores]] only)
 
{{expand list}}
 
{{expand list}}
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[[category:lithography]]

Latest revision as of 05:15, 20 July 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 500 nanometer (500 nm) lithography process is a full node semiconductor manufacturing process following the 600 nm process. Commercial integrated circuit manufacturing using 500 nm process began in 1992. 500 nm and was phased out and later replaced by 350 nm in 1995.

Industry[edit]

Fab
Process Name​
1st Production​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel AMD DEC Fujitsu Hitachi HP IBM TI Motorola National (BiCMOS)
P852 CS-24 CMOS-5 CMOS14C CMOS-5X HiPerMOS 1 ABiC V
1994 1993 1993 1994 1994 1996 1994 1995 1995
3 4 3 4 5 4 4
Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ Value 800 nm Δ
 ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
44 µm² 0.40x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x

DEC[edit]

See also: DEC's Process Technology History

DEC's half-micron process, CMOS-5, which was used for their microprocessors such as the Alpha 21164 used a Cabalt di-silicide in diffusion and poly with a channel length of 0.365 µm with a TOX of 9 nm along with 4 metal layers of AlCu (Aluminum Copper). The process had a Vtn/p = 0.5/-0.5 V and a supply voltage of 3.3 V.

500 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

500 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

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